📄 ssx31bdrv.h
字号:
#ifndef _SSX31BDRV_H_
#define _SSX31BDRV_H_
#define SSX31B_MAX_TBD 1
#define SSX31B_OPER_DH_PUBKEY 0x00
#define SSX31B_OPER_DH_PRIVKEY 0x01
#define SSX31B_OPER_DH_RSA_PUBKEY 0x02
#define SSX31B_OPER_DH_RSA_PRIVKEY 0x03
#define SSX31B_OPER_DH_DSA_SIGNAL 0x04
#define SSX31B_OPER_DH_DSA_AUTH 0x05
#define SSX31B_OPER_DH_MODULAR_ADD 0x40
#define SSX31B_OPER_DH_MODULAR_SUB 0x41
#define SSX31B_OPER_DH_MODULAR_MULTIPLY 0x42
#define SSX31B_OPER_DH_MODULAR 0x43
#define SSX31B_OPER_DH_MODULAR_PWR 0x44
#define SSX31B_OPER_DH_DUAL_MODULAR_PWR 0x45
#define SSX31B_OPER_SA_UPDATE 0x80
#define SSX31B_OPER_SA_GET 0x81
#define SSX31B_OPER_RANDOM_GET 0x84
#define SSX31B_OPER_IPSEC_WITHOUT_CTRL 0xC0
#define SSX31B_OPER_IPSEC_WITH_CTRL 0xC1
#define DMA1_ERR_MASK 0x1FFF
#define DMA1_ERR_BITS 16
#define MDA1_STATUS_OK 0
#define MDA1_ERR_LEN 0x0002
#define DMA1_ERR_OPER_CODE 0x0003
#define DMA1_ERR_PROC_TIMEOUT 0x0100
#define DMA1_ERR_LEN_NOTMATCH 0x0200
#define DMA1_ERR_INPUT_LEN 0x0400
#define DMA2_ERR_MASK 0x1FFF0000
#define DMA2_ERR_BITS 16
#define DMA2_ERR_ZERO 0x0001
#define DMA2_ERR_MODLEN 0x0002
#define DMA2_ERR_OPER_CODE 0x0004
#define DMA2_ERR_INDEX_ZERO 0x0008
#define DMA2_ERR_INDEX_ONE 0x0010
#define DMA2_ERR_PROC_TIMEOUT 0x0100
#define DMA2_ERR_LEN_NOTMATCH 0x0200
#define DMA2_ERR_INPUT_LEN 0x0400
#define DMA3_ENGING_ERR_MASK 0x7000
#define DMA3_ENGING_ERR_BITS 12
#define DMA3_ENGING_ERR_SUCESS 0x0
#define DMA3_ENGING_ERR_OPER_CODE 0x01
#define DMA3_ENGING_ERR_LEN 0x02
#define DMA3_ENGING_ERR_LEN_NOTMATCH 0x03
#define DMA3_ENGING_ERR_PROC_TIMEOUT 0x07
#define DMA3_SIGLE_ERR_MASK 0x70000000
#define DMA3_SIGLE_ERR_BITS 28
#define DMA3_SIGLE_ERR_BYTE_SOFT_TIMEOUT 0x04000000
#define DMA3_SIGLE_ERR_BYTE_HARD_TIMEOUT 0x02000000
#define DMA3_SIGLE_ERR_SEQNUM_FAIL 0x01000000
#define DMA3_SIGLE_ERR_ICV_FAIL 0x00800000
#define DMA3_SIGLE_ERR_PADDING 0x00400000
#define DMA3_SIGLE_ERR_PACK_STRUCTURE 0x00200000
#define DMA3_ERR_MASK 0x001F
#define DMA3_ERR_BITS 16
#define DMA3_ERR_SUCESS 0x00
#define DMA3_ERR_IP_FRAG 0x03
#define DMA3_ERR_PACK_STRUCTURE 0x11
#define DMA3_ERR_EXTHEAD 0x12
#define DMA3_ERR_INVALID_SA 0x13
#define DMA3_ERR_SPI_FAIL 0x14
#define DMA3_ERR_SEQNUM_FAIL 0x15
#define DMA3_ERR_BYTE_SOFT_TIMEOUT 0x16
#define DMA3_ERR_BYTE_HARD_TIMEOUT 0x17
#define DMA3_ERR_ALIGN 0x18
#define DMA3_ERR_ICV_FAIL 0x19
#define DMA3_ERR_PADDING 0x1B
/*主控寄存器*/
#define SSX31B_REG_MRID 0x0000
#define SSX31B_REG_SDRAM_CTRL 0x0004
#define SSX31B_REG_INT_CTRL0 0x0008
#define SSX31B_REG_INT_CTRL1 0x000C
#define SSX31B_REG_INT_CTRL2 0x0010
#define SSX31B_REG_INT_STAT 0x0014
#define SSX31B_REG_INT_MASK 0x0018
#define SSX31B_REG_CYC_CNT_1US 0x001C
#define SSX31B_REG_LBBMC 0x0020
#define SSX31B_REG_SDRAM_TEST 0x00F0
#define SSX31B_REG_GPIO 0x00F4
#define SSX31B_REG_CLK_ENABLE 0x0024
/*PLL控制寄存器*/
#define SSX31B_REG_PLL_RST 0x0200
#define SSX31B_REG_PLL0_CTRL 0x0204
#define SSX31B_REG_PLL1_CTRL 0x0208
/*IPSec侧寄存器*/
#define SSX31B_REG_PE_CTRL 0x1000
#define SSX31B_REG_AES_CTR_INIT 0x1004
#define SSX31B_REG_TIMER_HIGH 0x1008
#define SSX31B_REG_TIMER_LOW 0x100C
#define SSX31B_REG_LFSR_INIT_VAL 0x1020
#define SSX31B_REG_RX_PKT_CNT_H 0x1030
#define SSX31B_REG_RX_PKT_CNT_L 0x1034
#define SSX31B_REG_TX_PKT_CNT_H 0x1038
#define SSX31B_REG_TX_PKT_CNT_L 0x103C
/*DMA1控制寄存器*/
#define SSX31B_REG_BQBA1 0x2100
#define SSX31B_REG_BQS1 0x2104
#define SSX31B_REG_BQRP1 0x2108
#define SSX31B_REG_BQWP1 0x210C
#define SSX31B_REG_RQBA1 0x2110
#define SSX31B_REG_RQS1 0x2114
#define SSX31B_REG_RQRP1 0x2118
#define SSX31B_REG_RQWP1 0x211C
#define SSX31B_REG_DMACTRL1 0x2120
#define SSX31B_REG_PDLR1 0x2124
#define SSX31B_REG_BQTMOUT1 0x2128
/*DMA2控制寄存器*/
#define SSX31B_REG_BQBA2 0x2200
#define SSX31B_REG_BQS2 0x2204
#define SSX31B_REG_BQRP2 0x2208
#define SSX31B_REG_BQWP2 0x220C
#define SSX31B_REG_RQBA2 0x2210
#define SSX31B_REG_RQS2 0x2214
#define SSX31B_REG_RQRP2 0x2218
#define SSX31B_REG_RQWP2 0x221C
#define SSX31B_REG_DMACTRL2 0x2220
#define SSX31B_REG_PDLR2 0x2224
#define SSX31B_REG_BQTMOUT2 0x2228
/*DMA3控制寄存器*/
#define SSX31B_REG_BQBA3 0x2300
#define SSX31B_REG_BQS3 0x2304
#define SSX31B_REG_BQRP3 0x2308
#define SSX31B_REG_BQWP3 0x230C
#define SSX31B_REG_RQBA3 0x2310
#define SSX31B_REG_RQS3 0x2314
#define SSX31B_REG_RQRP3 0x2318
#define SSX31B_REG_RQWP3 0x231C
#define SSX31B_REG_DMACTRL3 0x2320
#define SSX31B_REG_PDLR3 0x2324
#define SSX31B_REG_BQTMOUT3 0x2328
/*RNG模块寄存器*/
#define SSX31B_REG_RNG_CTRL 0x4000
#define SSX31B_REG_RNG_STAT 0x4008
#define SSX31B_REG_RNG_TEST 0x400C
/*Local Bus模块寄存器*/
#define SSX31B_REG_LBUS_REG0 0x5000
#define SSX31B_REG_LBUS_REG1 0x5004
#define SSX31B_REG_LBUS_REG2 0x5008
#define SSX31B_REG_LBUS_REG3 0x500C
#define SSX31B_REG_LBUS_REG4 0x5010
#define SSX31B_REG_LBUS_REG5 0x5014
#define SSX31B_REG_LBUS_REG6 0x5018
#define SSX31B_REG_LBUS_REG7 0x501C
#define MASK_MRID_RST 0x80000000
#define SDRAM_CTRL_REFRESH_FREQ 500
#define MASK_SDRAM_CTRL_CAS_LATENCY 0x00070000
#define SDRAM_CTRL_CAS_LATENCY 3
#define MASK_SDRAM_CTRL_COL_BIT 0x00180000
#define SDRAM_CTRL_COL_BIT 0
#define SDRAM_CTRL_SDR_INIT (1 << 31)
#define INT_CTRL2_TIME_INTERVAL 1000
#define INT_CTRL2_TIME_COUNT_BIT 29
#define INT_CTRL2_PAKT_COUNT 0x0
#define INT_MASK_DMA1_PAKT_OPDONE 1
#define INT_MASK_DMA2_PAKT_OPDONE (1 << 8)
#define INT_MASK_DMA3_PAKT_OPDONE (1 << 16)
#define INT_MASK_DMA3_PROC_TMOUT (1 << 19)
#define INT_MASK_DMA2_PROC_TMOUT (1 << 11)
#define CYC_CNT_1US 66
#define CLOCK_ENABLE 3
#define PE_CTRL_ARBIT_ALG_SEL 0
#define PE_CTRL_ENGINE_SEL 0
#define PE_CTRL_ENGINE_SEL_BIT 8
#define PE_CTRL_PACK_FILTER (1 << 30)
#define DMA1_TIMEOUT_RD (1 << 16)
#define DMA1_TIMEOUT_DMA1 1
#define DMA2_TIMEOUT_RD (0xffff << 16)
#define DMA2_TIMEOUT_DMA2 0xffff
#define DMA3_TIMEOUT_RD (0xffff << 16)
#define DMA3_TIMEOUT_DMA3 0xffff
#define DMA1_CTRL_CHANNEL_ENABLE 1
#define DMA1_CTRL_CHANNEL_DISABLE 0
#define DMA1_CTRL_BURST_32 0
#define DMA1_CTRL_BURST_64 (1 << 1)
#define DMA1_CTRL_BURST_128 (2 << 1)
#define DMA1_CTRL_BURST_256 (3 << 1)
#define DMA1_CTRL_DESC_BYTEORDER_SWAP (1 << 5)
#define DMA2_CTRL_CHANNEL_ENABLE 1
#define DMA2_CTRL_BURST_256 (3 << 1)
#define DMA3_CTRL_CHANNEL_ENABLE 1
#define INT_STAT_DMA1_PACK_DONE 1
#define INT_STAT_DMA2_PACK_DONE (1 << 8 )
#define INT_STAT_DMA3_PACK_DONE (1 << 16)
#define CD_GATHER_ENABLE 1
#define CD_SCATTER_ENABLE 1
#define ICD_MID_SLICE 0x0000
#define ICD_LAST_SLICE 0xFF00
#define OCD_MID_SLICE 0x0000
#define OCD_LAST_SLICE 0xFF00
#define ICD_MID_SLICE_PKE 0x00
#define ICD_LAST_SLICE_PKE 0xFF
#define OCD_MID_SLICE_PKE 0x00
#define OCD_LAST_SLICE_PKE 0xFF
#define MAX_LEN_SSX31B_INS_PAD 257
#define MAX_LEN_SSX31B_INS_IPSEC_HEADER 64
#define IPSEC_MBUF_DATA_START 100
#define MAX_LEN_SSX31B_INS_IPSEC (MAX_LEN_SSX31B_INS_PAD + MAX_LEN_SSX31B_INS_IPSEC_HEADER + IPSEC_MBUF_DATA_START + 4)
#define MAX_MEM_LEN_SSX31B_DRVIER 2048
#define RCV_MEM_LEN_SSX31B_DRVIER 1648
#define SSX31B_MAX_GATHER 16
#define SSX31B_MAX_SCATTER 16
#define SSX31B_PE_CTRLWORD_IPSEC ( 1 << 26 )
#define SSX31B_PE_CTRLWORD_ANTIREPLAY ( 1 << 22 )
#define SSX31B_PE_CTRLWORD_FLOWCTRL ( 1 << 21 )
#define SSX31B_PE_CTRLWORD_PROCMODE 7
#define IPSEC_SECP_PKT_MODE_AHESP 3
#define SSX31B_PE_CTRLWORD (SSX31B_PE_CTRLWORD_IPSEC | SSX31B_PE_CTRLWORD_ANTIREPLAY | SSX31B_PE_CTRLWORD_FLOWCTRL)
#define SSX31B_PE_CTRLWORD_OUTBOUND ( 1 << 25 )
#define SSX31B_PE_CONTROLWORD_LEHGTN 4
#define SSX31B_PE_SA_NUM_LEHGTN 4
#define SSX31B_PE_HEADER_LEHGTN ( SSX31B_PE_CONTROLWORD_LEHGTN + SSX31B_PE_SA_NUM_LEHGTN )
#define SSX31B_MBUFQ_LEN 2048*2
#define SSX31B_SA_BDQUEUE_LEN 512
#define SSX31B_SA_RDQUEUE_LEN SSX31B_SA_BDQUEUE_LEN
#define SSX31B_IPSEC_BDQUEUE_LEN 1024
#define SSX31B_IPSEC_RDQUEUE_LEN SSX31B_IPSEC_BDQUEUE_LEN
#define SSX31B_PKE_BDQUEUE_LEN 512
#define SSX31B_PKE_RDQUEUE_LEN SSX31B_PKE_BDQUEUE_LEN
#define SSX31B_INT_MASK (INT_MASK_DMA3_PAKT_OPDONE | INT_MASK_DMA3_PROC_TMOUT)
typedef struct tagMBufQ
{
MBUF_S* pmbuf;
UCHAR flgHandleErr;
UCHAR* pucSource;
} MBufQ_S;
#ifdef BIG_ENDIAN
/* input context descriptor */
typedef struct tagSSX31BICD
{
ULONG ulInputPtr;
ULONG ulInputAttrib:16,
ulInputLen:16;
}SSX31B_ICD;
#else
typedef struct tagSSX31BICD
{
ULONG ulInputPtr;
ULONG ulInputLen:16,
ulInputAttrib:16;
}SSX31B_ICD;
#endif
#define SSX31B_ICD_LENGTH sizeof(SSX31B_ICD)
#ifdef BIG_ENDIAN
/* output context descriptor */
typedef struct tagSSX31BOcd
{
ULONG ulOutputPtr;
ULONG ulOutputAttrib:16,
ulOutputLen:16;
}SSX31B_OCD;
#else
typedef struct tagSSX31BOcd
{
ULONG ulOutputPtr;
ULONG ulOutputLen:16,
ulOutputAttrib:16;
}SSX31B_OCD;
#endif
#define SSX31B_OCD_LENGTH sizeof(SSX31B_OCD)
#ifdef BIG_ENDIAN
typedef struct tagSSX31BBasicBD
{
ULONG ulReserve:16,
ulOpCode:8,
ulFlag:8;
ULONG ulInputContext;
ULONG ulInputNum:5,
ulGatherEnable:1,
ulReserve1:6,
ulInputLength:20;
ULONG ulOutputContext;
ULONG ulOutputNum:5,
ulScatterEnable:1,
ulReserve2:6,
ulOutputLength:20;
ULONG ulID;
}SSX31B_BASIC_BD;
#else
typedef struct tagSSX31BBasicBD
{
ULONG ulFlag:8,
ulOpCode:8,
ulReserve:16;
ULONG ulInputContext;
ULONG ulInputLength:20,
ulReserve1:6,
ulGatherEnable:1,
ulInputNum:5;
ULONG ulOutputContext;
ULONG ulOutputLength:20,
ulReserve2:6,
ulScatterEnable:1,
ulOutputNum:5;
ULONG ulID;
}SSX31B_BASIC_BD;
#endif
#define SSX31B_BASIC_BD_LENGTH sizeof(SSX31B_BASIC_BD)
#ifdef BIG_ENDIAN
typedef struct tagSSX31BBasicRD
{
ULONG ulStatus:16,
ulOpCode:8,
ulFlag:8;
ULONG ulInputContext;
ULONG ulInputNum:5,
ulGatherEnable:1,
ulReserve1:6,
ulInputLength:20;
ULONG ulOutputContext;
ULONG ulOutputNum:5,
ulScatterEnable:1,
ulReserve2:6,
ulOutputLength:20;
ULONG ulID;
}SSX31B_BASIC_RD;
#else
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -