counter99.vhd

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-- 计数器控制,从0到99计数  每隔0.2S	
--liwei
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter99 is
	 Port (
	       clk:in std_logic;			  --50M的时钟频率；  
	       led_date : out std_logic_vector(7 downto 0);
		   seg_sel:out std_logic_vector(3 downto 0)
		  );
end counter99;
architecture Behavioral of counter99 is
signal  count: integer range 0 to 9;
signal  count10: integer range 0 to 9;
signal  led_date1 :std_logic_vector(7 downto 0);
signal  led_date10:std_logic_vector(7 downto 0);
signal clk_fresh : std_logic;
begin

process(clk)----200ms
variable cnt:integer range 0 to 10000000;
begin
    if clk'event and clk='1'  then   
	if cnt>10000000  then   cnt:=0; count<=count+1;
    else   cnt:=cnt+1;
    if count=10 then  count<=0;count10<=count10+1;
    if count10=9 then count10<=0;--有点疑惑，为什么count10=10不行
  end if;
  end if;
  end if;
  end if;
 end process;

process(clk)-- --1KHZ；用于扫描信号
variable cnt : integer range 0 to 50000;--定时1MS
begin
      if clk'event and clk='1' then cnt:=cnt+1;
           if cnt<25000 then clk_fresh<='1';
		     elsif cnt<50000 then clk_fresh<='0';
		     else cnt:=0;clk_fresh<='0';
		     end if;
      end if;
end process;

process(count)
 begin   
   case count is 
   when 0 =>led_date1<="11000000";--0   
   when 1 =>led_date1<="11111001";--1 
   when 2 =>led_date1<="10100100";--2
   when 3 =>led_date1<="10110000";--3 
   when 4 =>led_date1<="10011001";--4 
   when 5 =>led_date1<="10010010";--5 
   when 6 =>led_date1<="10000010";--6   
   when 7 =>led_date1<="11111000";--7   
   when 8 =>led_date1<="10000000";--8  
   when 9 =>led_date1<="10010000";--9  
   when others =>led_date1<="11111111";
   end case ; 
 end process;

 process(count10)
 begin   
   case count10 is 
   when 0 =>led_date10<="11000000";--0   
   when 1 =>led_date10<="11111001";--1 
   when 2 =>led_date10<="10100100";--2
   when 3 =>led_date10<="10110000";--3 
   when 4 =>led_date10<="10011001";--4 
   when 5 =>led_date10<="10010010";--5 
   when 6 =>led_date10<="10000010";--6   
   when 7 =>led_date10<="11111000";--7   
   when 8 =>led_date10<="10000000";--8  
   when 9 =>led_date10<="10010000";--9  
   when others =>led_date10<="11111111";
   end case ; 
 end process;

process(clk_fresh)--位选信号（扫描时间1MS）
variable cnt : std_logic_vector(1 downto 0);
begin
  if (clk_fresh'event and clk_fresh='1') then 
      cnt:=cnt+1;
		 if cnt="01" then 
				seg_sel<="0001";
				led_date<=led_date1;	   --
		 elsif cnt="10" then 
				seg_sel<="0010";
				led_date<=led_date10;   	--
		 else   seg_sel<="0000";
	    end if;
	  
  end if;
end process;

end Behavioral;