mulcsvsgn.vhd

这是很全的标准库啊

-------------------------------------------------------------------------------
-- Title       : Signed carry-save multiplier
-- Project     : VHDL Library of Arithmetic Units
-------------------------------------------------------------------------------
-- File        : MulCsvSgn.vhd
-- Author      : Reto Zimmermann  <[e-mail]>
-- Company     : Integrated Systems Laboratory, ETH Zurich
-- Date        : 1998/01/19
-------------------------------------------------------------------------------
-- Copyright (c) 1998 Integrated Systems Laboratory, ETH Zurich
-------------------------------------------------------------------------------
-- Description :
-- Multiplier for signed numbers with one input operand and the
-- result in carry-save number representation (Brown). First adds two
-- numbers, then multiplies the result with the multiplicand without
-- performing final addition. Result is only valid if sum of
-- carry-save input operands does not overflow.
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library arith_lib;
use arith_lib.arith_lib.all;

-------------------------------------------------------------------------------

entity MulCsvSgn is

  generic (widthX : positive := 8;     -- word width of XS, XC (<= widthY)
	   widthY : positive := 8;     -- word width of Y
	   speed : speedType := fast);  -- performance parameter

  port (XS, XC : in std_logic_vector(widthX-1 downto 0);  -- multipliers
	Y : in std_logic_vector(widthY-1 downto 0);  -- multiplicand
        PS, PC : out std_logic_vector(widthX+widthY-1 downto 0));  -- product

end MulCsvSgn;

-------------------------------------------------------------------------------

architecture Behavioral of MulCsvSgn is

  signal XSuns, XCuns : signed(widthX-1 downto 0);  -- signed
  signal Yuns : signed(widthY-1 downto 0);  -- signed
  signal PSuns : signed(widthX+widthY-1 downto 0);  -- signed

begin

  -- type conversion: std_logic_vector -> signed
  XSuns <= signed(XS);
  XCuns <= signed(XC);
  Yuns <= signed(Y);

  -- addition and multiplication
  PSuns <= (XSuns + XCuns) * Yuns;

  -- type conversion: signed -> std_logic_vector
  PS <= std_logic_vector(PSuns);
  PC <= (others => '0');

end Behavioral;

-------------------------------------------------------------------------------

architecture Structural of MulCsvSgn is 

						-- partial products
  signal PP : std_logic_vector((widthX+1)*(widthX+widthY)-1 downto 0);
						-- intermediate sum/carry bits
  signal ST, CT : std_logic_vector(widthX+widthY-1 downto 0); 

begin

  -- generation of partial products
  ppGen : AddMulPPGenSgn
    generic map (widthX, widthY)
    port map (XS, XC, Y, PP);

  -- carry-save addition of partial products
  csvAdd : AddMopCsv
    generic map (widthX+widthY, widthX+1, speed)
    port map (PP, PS, PC);

end Structural;

-------------------------------------------------------------------------------