cpr.vhd

Cadence的VHDL运算库包

-------------------------------------------------------------------------------
-- Title       : (m,2)-compressor (for carry-save adders)
-- Project     : VHDL Library of Arithmetic Units
-------------------------------------------------------------------------------
-- File        : Cpr.vhd
-- Author      : Reto Zimmermann  <[e-mail]>
-- Company     : Integrated Systems Laboratory, ETH Zurich
-- Date        : 1997/11/17
-------------------------------------------------------------------------------
-- Copyright (c) 1998 Integrated Systems Laboratory, ETH Zurich
-------------------------------------------------------------------------------
-- Description :
-- (m,2)-compressor adds m bits. Result is 2 bits, one sum bit S and one carry
-- bit C. m-2 intermediate carries are forwarded to next higher compressor
-- (note: many parallel compressors form a multi-operand carry-save adder).
-- Composed of full-adders arranged linearly or in tree structure.
-- Condition: m >= 4.
-- Linear structure: structure depth = # operands - 2
-- Tree structure:
--   structure depth :   2   3   4   5   6   7   8   9  10  11  12
--   # operands      :   4   6   9  13  19  28  42  63  94 141 211
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
library arith_lib;
use arith_lib.arith_lib.all;

-------------------------------------------------------------------------------

entity Cpr is

  generic (depth : positive := 4;	-- number of input bits
	   speed : speedType := fast);  -- performance parameter

  port (A : in std_logic_vector(depth-1 downto 0);  -- input bits
        CI : in std_logic_vector(depth-4 downto 0);  -- intermediate carries in
	S, C : out std_logic;  		-- sum and carry out
        CO : out std_logic_vector(depth-4 downto 0));  -- interm. carries out

end Cpr;

-------------------------------------------------------------------------------

architecture Structural of Cpr is 
  
					-- FIFO vector of internal signals
  signal F : std_logic_vector(depth+2*(depth-2)-1 downto 0);
  signal CIT, COT : std_logic_vector(depth-3 downto 0);  -- temp. int. carries

begin

  -- put input bits to beginning of FIFO vector
  F(depth-1 downto 0) <= A;

  -- temporary intermediate carries in
  CIT(depth-3 downto 0) <= '0' & CI(depth-4 downto 0);

  -- compressor with linear structure
  slowCpr : if speed = slow generate

    -- first full-adder
    fa0 : FullAdder
      port map (F(0), F(1), F(2), F(depth), COT(0));

    -- linear arrangement of full-adders
    linear : for i in 1 to depth-3 generate
      fa : FullAdder
	port map (F(i+2), CIT(i-1), F(depth+(i-1)*2), F(depth+i*2), COT(i));
    end generate linear;

  end generate slowCpr;

  -- compressor with tree structure
  fastCpr : if speed /= slow generate

    -- tree arrangement of full-adders:
    tree : for i in 0 to depth-3 generate
      -- take inputs from beginning of FIFO vector
      -- attach sum output to end of FIFO vector
      -- put carry output to intermediate carry-out
      fa : FullAdder
	port map (F(i*3), F(i*3+1), F(i*3+2), F(depth+i*2), COT(i));
      -- attach intermediate carry-in to end of FIFO vector
      F(depth+i*2+1) <= CIT(i);
    end generate tree;

  end generate fastCpr;

  -- intermediate carries out
  CO <= COT(depth-4 downto 0);

  -- sum and carry out
  S <= F(3*depth-6);
  C <= COT(depth-3);

end Structural;

-------------------------------------------------------------------------------