testbenchexample.vhd

Cadence的VHDL运算库包

-------------------------------------------------------------------------------
-- Title       : Example test bench
-- Project     : VHDL Library of Arithmetic Units
-------------------------------------------------------------------------------
-- File        : TestBenchExample.vhd
-- Author      : Reto Zimmermann  <[e-mail]>
-- Company     : Integrated Systems Laboratory, ETH Zurich
-- Date        : 1997/11/04
-------------------------------------------------------------------------------
-- Copyright (c) 1998 Integrated Systems Laboratory, ETH Zurich
-------------------------------------------------------------------------------
-- Description :
-- Example test bench for exhaustive simulation of the `Example' circuit.
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
library synergy;  use synergy.signed_arith.all;
library arith_lib;
use arith_lib.arith_lib.all;

-------------------------------------------------------------------------------

entity TestBenchExample is
  
end TestBenchExample;

-------------------------------------------------------------------------------

architecture Exhaustive of TestBenchExample is

  constant width : positive := 8;
  constant speed : speedType := fast;

  for s1 : Add use entity arith_lib.Add(Structural);
  for b1 : Add use entity arith_lib.Add(Behavioral);

  signal A, B, SS, SB : std_logic_vector(width-1 downto 0);

begin

  s1 : Add
    generic map (width, speed)
    port map (A, B, SS);

  b1 : Add
    generic map (width, speed)
    port map (A, B, SB);

  run : process
  begin
    for ai in 0 to 2**width-1 loop
      A <= std_logic_vector(conv_unsigned(ai, width));
      for bi in 0 to 2**width-1 loop
        B <= std_logic_vector(conv_unsigned(bi, width));
        wait for 100 ns;
        if SS /= SB then
          assert false report ">>> error occurred <<<" severity failure;
        end if;
      end loop;
    end loop;
    
    assert false report "no errors" severity note;
    wait;
  end process run;

end Exhaustive;

-------------------------------------------------------------------------------