cmpeq.vhd

Cadence的VHDL运算库包

-------------------------------------------------------------------------------
-- Title       : Equality comparator
-- Project     : VHDL Library of Arithmetic Units
-------------------------------------------------------------------------------
-- File        : CmpEQ.vhd
-- Author      : Reto Zimmermann  <[e-mail]>
-- Company     : Integrated Systems Laboratory, ETH Zurich
-- Date        : 1997/12/28
-------------------------------------------------------------------------------
-- Copyright (c) 1998 Integrated Systems Laboratory, ETH Zurich
-------------------------------------------------------------------------------
-- Description :
-- Equality comparison of two numbers.
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
library synergy;  use synergy.signed_arith.all;
library arith_lib;
use arith_lib.arith_lib.all;

-------------------------------------------------------------------------------

entity CmpEQ is

  generic (width : positive := 8);  	-- word width

  port (A, B : in std_logic_vector(width-1 downto 0);  -- operands
	EQ : out std_logic);		-- equal flag

end CmpEQ;

-------------------------------------------------------------------------------

architecture Behavioral of CmpEQ is

  signal Auns, Buns : unsigned(width-1 downto 0);  -- unsigned

begin

  -- type conversion: std_logic_vector -> unsigned
  Auns <= unsigned(A);
  Buns <= unsigned(B);

  -- equality comparison
  EQ <= '1' when Auns = Buns else '0';

end Behavioral;

-------------------------------------------------------------------------------

architecture Structural of CmpEQ is

  signal EQT : std_logic_vector(width-1 downto 0);  -- temp.

begin

  -- comparison of individual bits
  cmpBit : for i in 0 to width-1 generate
    EQT(i) <= not (A(i) xor B(i));
  end generate cmpBit;

  -- AND all comparison bits
  cmpFlag : RedAnd
    generic map (width)
    port map (EQT, EQ);

end Structural;

-------------------------------------------------------------------------------