addsub.vhd

Cadence的VHDL运算库包

-------------------------------------------------------------------------------
-- Title       : Parallel-prefix adder-subtractor
-- Project     : VHDL Library of Arithmetic Units
-------------------------------------------------------------------------------
-- File        : AddSub.vhd
-- Author      : Reto Zimmermann  <[e-mail]>
-- Company     : Integrated Systems Laboratory, ETH Zurich
-- Date        : 1997/11/04
-------------------------------------------------------------------------------
-- Copyright (c) 1998 Integrated Systems Laboratory, ETH Zurich
-------------------------------------------------------------------------------
-- Description :
-- Binary adder-subtractor using parallel-prefix carry-lookahead logic.
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
library synergy;  use synergy.signed_arith.all;
library arith_lib;
use arith_lib.arith_lib.all;

-------------------------------------------------------------------------------

entity AddSub is

  generic (width : positive := 8;  	-- word width
	   speed : speedType := fast);  -- performance parameter

  port (A, B : in std_logic_vector(width-1 downto 0);  -- operands
        SUB : in std_logic;  		-- subtraction enable
	S : out std_logic_vector(width-1 downto 0));  -- sum

end AddSub;

-------------------------------------------------------------------------------

architecture Behavioral of AddSub is

  signal Auns, Buns, Suns : unsigned(width-1 downto 0);  -- unsigned

begin

  -- type conversion: std_logic_vector -> unsigned
  Auns <= unsigned(A);
  Buns <= unsigned(B);

  -- addition or subtraction
  Suns <= Auns + Buns when SUB = '0' else
          Auns - Buns;

  -- type conversion: unsigned -> std_logic_vector
  S <= std_logic_vector(Suns);

end Behavioral;

-------------------------------------------------------------------------------

architecture Structural of AddSub is 

  signal BI : std_logic_vector(width-1 downto 0);  -- B inverted
  signal GI, PI : std_logic_vector(width-1 downto 0);  -- prefix gen./prop. in
  signal GO, PO : std_logic_vector(width-1 downto 0);  -- prefix gen./prop. out
  signal PT : std_logic_vector(width-1 downto 0);  -- adder propagate temp

begin

  -- invert B for subtraction
  BI <= B xor (width-1 downto 0 => SUB);
  
  -- calculate prefix input generate/propagate signal (0)
  GI(0) <= (A(0) and BI(0)) or (A(0) and SUB) or (BI(0) and SUB);
  PI(0) <= '0';
  -- calculate adder propagate signal (0) (PT = A xor B)
  PT(0) <= A(0) xor BI(0);
  -- calculate prefix input generate/propagate signals (1 to width-1)
  preproc : for i in width-1 downto 1 generate
    GI(i) <= A(i) and BI(i);
    PI(i) <= A(i) or BI(i);
    -- calculate adder propagate signal (1 to width-1) (PT = A xor B)
    PT(i) <= not GI(i) and PI(i);
  end generate preproc;

  -- calculate prefix output generate/propagate signals
  prefix : PrefixAndOr
    generic map (width, speed)
    port map (GI, PI, GO, PO);

  -- calculate sum bits
  S <= PT xor GO(width-2 downto 0) & SUB;

end Structural;

-------------------------------------------------------------------------------