mulppgensgn.vhd

Cadence的VHDL运算库包

-------------------------------------------------------------------------------
-- Title       : Partial-product generator for signed multiplier
-- Project     : VHDL Library of Arithmetic Units
-------------------------------------------------------------------------------
-- File        : MulPPGenSgn.vhd
-- Author      : Reto Zimmermann  <[e-mail]>
-- Company     : Integrated Systems Laboratory, ETH Zurich
-- Date        : 1997/11/12
-------------------------------------------------------------------------------
-- Copyright (c) 1998 Integrated Systems Laboratory, ETH Zurich
-------------------------------------------------------------------------------
-- Description :
-- Partial-product generator for signed multiplier (Baugh-Wooley).
--
-- Partial products and correction terms for 4x4-bit signed multiplication:
--
--      0         0         0         0 ~x(0)y(3)  x(0)y(2)  x(0)y(1)  x(0)y(0)
--      0         0         0 ~x(1)y(3)  x(1)y(2)  x(1)y(1)  x(1)y(0)         0
--      0         0 ~x(2)y(3)  x(2)y(2)  x(2)y(1)  x(2)y(0)         0         0
--      0  x(3)y(3) x(3)~y(2) x(3)~y(1) x(3)~y(0)         0         0         0
--      0     ~x(3)         0         0      x(3)         0         0         0
--      1     ~y(3)         0         0      y(3)         0         0         0
-------------------------------------------------------------------------------
--   p(7)      p(6)      p(5)      p(4)      p(3)      p(2)      p(1)      p(0)
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
library arith_lib;
use arith_lib.arith_lib.all;

-------------------------------------------------------------------------------

entity MulPPGenSgn is

  generic (widthX : positive := 8;	-- word width of X
	   widthY : positive := 8);	-- word width of Y

  port (X : in std_logic_vector(widthX-1 downto 0);  -- multiplier
	Y : in std_logic_vector(widthY-1 downto 0);  -- multiplicand
						     -- partial products
        PP : out std_logic_vector((widthX+2)*(widthX+widthY)-1 downto 0));

end MulPPGenSgn;

-------------------------------------------------------------------------------

architecture Structural of MulPPGenSgn is 

  constant widthP : positive := widthX+widthY;  -- width of single part. prod.

begin

  ppGen : process (X, Y)
    variable ppt : std_logic_vector((widthX+2)*widthP-1 downto 0);
  begin

    -- defaults
    ppt := (others => '0');

    -- partial products x(i)y(k)
    for i in 0 to widthX-2 loop
      for k in 0 to widthY-2 loop
	ppt(i*widthP+i+k) := X(i) and Y(k);
      end loop;
      ppt(i*widthP+i+widthY-1) := not X(i) and Y(widthY-1);
    end loop;
    for k in 0 to widthY-2 loop
      ppt((widthX-1)*widthP+(widthX-1)+k) := X(widthX-1) and not Y(k);
    end loop;
    ppt((widthX-1)*widthP+(widthX-1)+widthY-1) := X(widthX-1) and Y(widthY-1);

    -- correction terms
    ppt((widthX+1)*widthP-2) := not X(widthX-1);
    ppt(widthX*widthP+widthX-1) := X(widthX-1);
    ppt((widthX+2)*widthP-1) := '1';
    ppt((widthX+2)*widthP-2) := not Y(widthY-1);
    ppt((widthX+1)*widthP+widthY-1) := Y(widthY-1);
  
    PP <= ppt;

  end process ppGen;

end Structural;

-------------------------------------------------------------------------------