addmopcsv.vhd

Cadence的VHDL运算库包

-------------------------------------------------------------------------------
-- Title       : Carry-save multi-operand adder
-- Project     : VHDL Library of Arithmetic Units
-------------------------------------------------------------------------------
-- File        : AddMopCsv.vhd
-- Author      : Reto Zimmermann  <[e-mail]>
-- Company     : Integrated Systems Laboratory, ETH Zurich
-- Date        : 1997/11/13
-------------------------------------------------------------------------------
-- Copyright (c) 1998 Integrated Systems Laboratory, ETH Zurich
-------------------------------------------------------------------------------
-- Description :
-- Carry-save adder using linear- or tree-structured (m,2)-compressors.
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
library synergy;  use synergy.signed_arith.all;
library arith_lib;
use arith_lib.arith_lib.all;

-------------------------------------------------------------------------------

entity AddMopCsv is

  generic (width : positive := 8;	-- word width
	   depth : positive := 4;	-- number of operands
	   speed : speedType := fast);  -- performance parameter

  port (A : in std_logic_vector(depth*width-1 downto 0);  -- operands
	S, C : out std_logic_vector(width-1 downto 0));  -- sum / carry vector

end AddMopCsv;

-------------------------------------------------------------------------------

architecture Behavioral of AddMopCsv is

  signal Auns : unsigned(depth*width-1 downto 0);  -- unsigned
  signal Suns : unsigned(width-1 downto 0);  -- unsigned

begin

  -- type conversion: std_logic_vector -> unsigned
  Auns <= unsigned(A);

  -- multi-operand addition
  add : process (A)
    variable s : unsigned(width-1 downto 0);
  begin
    s := (others => '0');
    for i in 0 to depth-1 loop
      s := s + Auns(i*(width+1)-1 downto i*width);
    end loop;
    Suns <= s;
  end process add;

  -- type conversion: unsigned -> std_logic_vector
  S <= std_logic_vector(Suns);
  C <= (others => '0');

end Behavioral;

-------------------------------------------------------------------------------

architecture Structural of AddMopCsv is 

  signal AT : std_logic_vector(depth*width-1 downto 0);  -- re-arranged inputs
							-- intermediate carries
  signal CI : std_logic_vector((depth-3)*(width+1)-1 downto 0);
  signal CT : std_logic_vector(width-1 downto 0);  -- unshifted output carries

begin

  -- re-arrange input bits: group bits of same magnitude
  swizzle : process (A)
  begin
    for k in depth-1 downto 0 loop
      for i in width-1 downto 0 loop
        AT(i*depth + k) <= A(k*width + i);
      end loop;
    end loop;
  end process swizzle;

  -- set intermediate carries into first slice
--synopsys_bug  CI(depth-4 downto 0) <= (others => '0');
  synopsys_bug : for i in depth-4 downto 0 generate
    CI(i) <= '0';
  end generate synopsys_bug;

  -- carry-save addition using (m,2) compressor bit-slices
  bits : for i in 0 to width-1 generate
    slice : Cpr
      generic map (depth, speed)
      port map (AT((i+1)*depth-1 downto i*depth),
		CI((i+1)*(depth-3)-1 downto i*(depth-3)),
		S(i), CT(i),
		CI((i+2)*(depth-3)-1 downto (i+1)*(depth-3)));
  end generate bits;

  -- shift left output carries by one position
  C <= CT(width-2 downto 0) & '0'; 

end Structural;

-------------------------------------------------------------------------------