addmulppgensgn.vhd

Cadence的VHDL运算库包

-------------------------------------------------------------------------------
-- Title       : Partial-product generator for signed adder-multiplier
-- Project     : VHDL Library of Arithmetic Units
-------------------------------------------------------------------------------
-- File        : AddMulPPGenSgn.vhd
-- Author      : Reto Zimmermann  <[e-mail]>
-- Company     : Integrated Systems Laboratory, ETH Zurich
-- Date        : 1997/11/19
-------------------------------------------------------------------------------
-- Copyright (c) 1998 Integrated Systems Laboratory, ETH Zurich
-------------------------------------------------------------------------------
-- Description :
-- Partial-product generator for unsigned adder-multiplier (Braun) (i.e.
-- multiplier is sum of two input operands). Sign treated by sign extension
-- (no Baugh-Wooley multiplier).
-- 
-- Partial products for 4x4-bit signed multiplication (using sign extension):
--
--  x(0)y(3) x(0)y(3) x(0)y(3) x(0)y(3) x(0)y(3) x(0)y(2) x(0)y(1) x(0)y(0)
--  x(1)y(3) x(1)y(3) x(1)y(3) x(1)y(3) x(1)y(2) x(1)y(1) x(1)y(0)        0
--  x(2)y(3) x(2)y(3) x(2)y(3) x(2)y(2) x(2)y(1) x(2)y(0)        0        0
--  x(3)y(3) x(3)y(3) x(3)y(2) x(3)y(1) x(3)y(0)        0        0        0
-------------------------------------------------------------------------------
--      p(7)     p(6)     p(5)     p(4)     p(3)     p(2)     p(1)     p(0)
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
library arith_lib;
use arith_lib.arith_lib.all;

-------------------------------------------------------------------------------

entity AddMulPPGenSgn is

  generic (widthX : positive := 8;	-- word width of XS, XC
	   widthY : positive := 8);	-- word width of Y

  port (XS, XC : in std_logic_vector(widthX-1 downto 0);  -- multipliers
	Y : in std_logic_vector(widthY-1 downto 0);  -- multiplicand
						     -- partial products
        PP : out std_logic_vector((widthX+1)*(widthX+widthY)-1 downto 0));

end AddMulPPGenSgn;

-------------------------------------------------------------------------------

architecture Structural of AddMulPPGenSgn is 

  constant widthP : positive := widthX+widthY;  -- width of single part. prod.

  signal M1, M2 : std_logic_vector(widthX-1 downto 0);  -- recoded multiplier
  signal YT, YBT : std_logic_vector(widthY+1 downto 0);  -- expanded Y

begin

  -- recode multiplier
  M1 <= XS xor XC;
  M2 <= XS and XC;

  -- expand Y (used for term 2y)
  YT <= Y(widthY-1) & Y(widthY-1 downto 0) & '0';
  YBT <= not Y(widthY-1) & not Y(widthY-1 downto 0) & '0';

  ppGen : process (M1, M2, YT, YBT)
    variable ppt : std_logic_vector((widthX+1)*widthP-1 downto 0);
  begin

    -- defaults
    ppt := (others => '0');

    -- partial products (xs(i)+xc(i))y(k):
    --   if M1 = '1' then y(i)
    --   if M2 = '1' then 2y(i)
    for i in 0 to widthX-2 loop
      for k in 0 to widthY loop
	ppt(i*widthP+i+k) := (M1(i) and YT(k+1)) or (M2(i) and YT(k));
      end loop;
      -- sign extension
      for k in widthY+1 to widthY+widthX-1-i loop
	ppt(i*widthP+i+k) := (M1(i) or M2(i)) and YT(widthY);
      end loop;
    end loop;
    -- negation of last partial product
    for k in 0 to widthY loop
      ppt((widthX-1)*widthP+widthX-1+k) :=
	(M1(widthX-1) and YBT(k+1)) or (M2(widthX-1) and YBT(k));
    end loop;
    -- carry-in for 2's complement of last partial product
    ppt(widthX*widthP+widthX-1) := M1(widthX-1);
    ppt(widthX*widthP+widthX) := M2(widthX-1);

    PP <= ppt;

  end process ppGen;

end Structural;

-------------------------------------------------------------------------------