cmpge.vhd

Cadence的VHDL运算库包

-------------------------------------------------------------------------------
-- Title       : Magnitude comparator
-- Project     : VHDL Library of Arithmetic Units
-------------------------------------------------------------------------------
-- File        : CmpGE.vhd
-- Author      : Reto Zimmermann  <[e-mail]>
-- Company     : Integrated Systems Laboratory, ETH Zurich
-- Date        : 1997/12/28
-------------------------------------------------------------------------------
-- Copyright (c) 1998 Integrated Systems Laboratory, ETH Zurich
-------------------------------------------------------------------------------
-- Description :
-- Magnitude (i.e. greater equal) comparison of two numbers by a simplified
-- subtraction. 
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
library synergy;  use synergy.signed_arith.all;
library arith_lib;
use arith_lib.arith_lib.all;

-------------------------------------------------------------------------------

entity CmpGE is

  generic (width : positive := 8;  	-- word width
	   speed : speedType := fast);  -- performance parameter

  port (A, B : in std_logic_vector(width-1 downto 0);  -- operands
	GE : out std_logic);		-- equal flag

end CmpGE;

-------------------------------------------------------------------------------

architecture Behavioral of CmpGE is

  signal Auns, Buns : unsigned(width-1 downto 0);  -- unsigned

begin

  -- type conversion: std_logic_vector -> unsigned
  Auns <= unsigned(A);
  Buns <= unsigned(B);

  -- equality comparison
  GE <= '1' when Auns >= Buns else '0';

end Behavioral;

-------------------------------------------------------------------------------

architecture Structural of CmpGE is

  signal GI, PI : std_logic_vector(width-1 downto 0);  -- prefix gen./prop. in
  signal GO, PO : std_logic_vector(width-1 downto 0);  -- prefix gen./prop. out

begin

  -- calculate prefix input generate/propagate signal (0)
  GI(0) <= A(0) or not B(0);
  PI(0) <= not (A(0) xor B(0));

  -- calculate prefix input generate/propagate signals (1 to width-1)
  preproc : for i in width-1 downto 1 generate
    GI(i) <= A(i) and not B(i);
    PI(i) <= not (A(i) xor B(i));
  end generate preproc;

  -- calculate prefix output generate/propagate signals
  prefix : PrefixAndOr
    generic map (width, speed)
    port map (GI, PI, GO, PO);

  -- result
  GE <= GO(width-1);

end Structural;

-------------------------------------------------------------------------------