arith_lib.vhd

Cadence的VHDL运算库包

  component AddMulSgn
    generic (widthX : positive;
	     widthY : positive;
	     speed : speedType);
    port (XS, XC : in std_logic_vector(widthX-1 downto 0);
	  Y : in std_logic_vector(widthY-1 downto 0);
	  P : out std_logic_vector(widthX+widthY-1 downto 0));
  end component;

  component MulCsvUns
    generic (widthX : positive;
	     widthY : positive;
	     speed : speedType);
    port (XS, XC : in std_logic_vector(widthX-1 downto 0);
	  Y : in std_logic_vector(widthY-1 downto 0);
	  PS, PC : out std_logic_vector(widthX+widthY-1 downto 0));
  end component;

  component MulCsvSgn
    generic (widthX : positive;
	     widthY : positive;
	     speed : speedType);
    port (XS, XC : in std_logic_vector(widthX-1 downto 0);
	  Y : in std_logic_vector(widthY-1 downto 0);
	  PS, PC : out std_logic_vector(widthX+widthY-1 downto 0));
  end component;

  component SqrUns
    generic (width : positive;
	     speed : speedType);
    port (X : in std_logic_vector(width-1 downto 0);
	  P : out std_logic_vector(2*width-1 downto 0));
  end component;

  component SqrSgn
    generic (width : positive;
	     speed : speedType);
    port (X : in std_logic_vector(width-1 downto 0);
	  P : out std_logic_vector(2*width-1 downto 0));
  end component;

  -----------------------------------------------------------------------------
  -- Dividers / Square Root Extractors
  -----------------------------------------------------------------------------
  component DivArrUns
    generic (widthX : positive;
	     widthY : positive);
    port (X : in std_logic_vector(widthX-1 downto 0);
	  Y : in std_logic_vector(widthY-1 downto 0);
	  Q : out std_logic_vector(widthX-widthY downto 0);
	  R : out std_logic_vector(widthY-1 downto 0));
  end component;

  component SqrtArrUns
    generic (widthX : positive);
    port (X : in std_logic_vector(widthX-1 downto 0);
	  Q : out std_logic_vector((widthX+1)/2-1 downto 0);
	  R : out std_logic_vector((widthX+1)/2-1 downto 0));
  end component;

  -----------------------------------------------------------------------------
  -- Miscellaneous
  -----------------------------------------------------------------------------
  component Bin2Gray
    generic (width : positive);
    port (B : in std_logic_vector(width-1 downto 0);
	  G : out std_logic_vector(width-1 downto 0));
  end component;
  
  component Gray2Bin
    generic (width : positive;
	     speed : speedType);
    port (G : in std_logic_vector(width-1 downto 0);
	  B : out std_logic_vector(width-1 downto 0));
  end component;
  
  component CmpEQ
    generic (width : positive);
    port (A, B : in std_logic_vector(width-1 downto 0);
	  EQ : out std_logic);
  end component;
  
  component CmpGE
    generic (width : positive;
	     speed : speedType);
    port (A, B : in std_logic_vector(width-1 downto 0);
	  GE : out std_logic);
  end component;
  
  component CmpEQGE
    generic (width : positive;
	     speed : speedType);
    port (A, B : in std_logic_vector(width-1 downto 0);
	  EQ, GE : out std_logic);
  end component;
  
  component AllZeroDet
    generic (width : positive);
    port (A : in std_logic_vector(width-1 downto 0);
	  Z : out std_logic);
  end component;
  
  component AllOneDet
    generic (width : positive);
    port (A : in std_logic_vector(width-1 downto 0);
	  Z : out std_logic);
  end component;
  
  component LeadZeroDet
    generic (width : positive;
	     speed : speedType);
    port (A : in std_logic_vector(width-1 downto 0);
	  Z : out std_logic_vector(width-1 downto 0));
  end component;
  
  component LeadOneDet
    generic (width : positive;
	     speed : speedType);
    port (A : in std_logic_vector(width-1 downto 0);
	  Z : out std_logic_vector(width-1 downto 0));
  end component;
  
  component LeadSignDet
    generic (width : positive;
	     speed : speedType);
    port (A : in std_logic_vector(width-1 downto 0);
	  Z : out std_logic_vector(width-1 downto 0));
  end component;
  
  component SumZeroDet
    generic (width : positive);
    port (A, B : in std_logic_vector(width-1 downto 0);
	  CI : in std_logic;
	  Z : out std_logic);
  end component;
  
--compass compile_off
  component Log2
    generic (width : positive;
	     speed : speedType);
    port (A : in std_logic_vector(width-1 downto 0);
	  Z : out std_logic_vector(log2ceil(width)-1 downto 0));
  end component;
--compass compile_on

  -----------------------------------------------------------------------------
  -- Subcomponents
  -----------------------------------------------------------------------------
  component PrefixAndOr
    generic (width : positive;
	     speed : speedType);
    port (GI, PI : in std_logic_vector(width-1 downto 0);
	  GO, PO : out std_logic_vector(width-1 downto 0));
  end component;

  component PrefixAndOrCfast
    generic (width : positive;
	     speed : speedType);
    port (GI, PI : in std_logic_vector(width-1 downto 0);
	  CI : in std_logic;
	  GO, PO : out std_logic_vector(width-1 downto 0));
  end component;

  component PrefixAndOrCendaround
    generic (width : positive;
	     speed : speedType);
    port (GI, PI : in std_logic_vector(width-1 downto 0);
	  CI : in std_logic;
	  GO, PO : out std_logic_vector(width-1 downto 0);
	  CO : out std_logic);
  end component;

  component PrefixAnd
    generic (width : positive;
	     speed : speedType);
    port (PI : in std_logic_vector(width-1 downto 0);
	  PO : out std_logic_vector(width-1 downto 0));
  end component;

  component PrefixOr
    generic (width : positive;
	     speed : speedType);
    port (PI : in std_logic_vector(width-1 downto 0);
	  PO : out std_logic_vector(width-1 downto 0));
  end component;

  component PrefixXor
    generic (width : positive;
	     speed : speedType);
    port (PI : in std_logic_vector(width-1 downto 0);
	  PO : out std_logic_vector(width-1 downto 0));
  end component;


  component Cpr
    generic (depth : positive;
	     speed : speedType);
    port (A : in std_logic_vector(depth-1 downto 0);
          CI : in std_logic_vector(depth-4 downto 0);
          S, C : out std_logic;
          CO : out std_logic_vector(depth-4 downto 0));
  end component;

--compass compile_off
  component Cnt
    generic (depth : positive;
	     speed : speedType);
    port (A : in std_logic_vector(depth-1 downto 0);
          S : out std_logic_vector(log2floor(depth) downto 0));
  end component;
--compass compile_on

  component CntSlice
    generic (depth : positive;
	     speed : speedType);
    port (A : in std_logic_vector(depth-1 downto 0);
          S : out std_logic;
          CO : out std_logic_vector(depth/2-1 downto 0));
  end component;


  component AddMod2Np1Csv
    generic (width : positive;
             depth : positive);
    port (A : std_logic_vector(depth*width-1 downto 0);
          S, C : out std_logic_vector(width-1 downto 0));
  end component;


  component MulPPGenUns
    generic (widthX : positive;
	     widthY : positive);
    port (X : in std_logic_vector(widthX-1 downto 0);
	  Y : in std_logic_vector(widthY-1 downto 0);
	  PP : out std_logic_vector(widthX*(widthX+widthY)-1 downto 0));
  end component;

  component MulPPGenSgn
    generic (widthX : positive;
	     widthY : positive);
    port (X : in std_logic_vector(widthX-1 downto 0);
	  Y : in std_logic_vector(widthY-1 downto 0);
	  PP : out std_logic_vector((widthX+2)*(widthX+widthY)-1 downto 0));
  end component;

  component AddMulPPGenUns
    generic (widthX : positive;
	     widthY : positive);
    port (XS, XC : in std_logic_vector(widthX-1 downto 0);
	  Y : in std_logic_vector(widthY-1 downto 0);
	  PP : out std_logic_vector(widthX*(widthX+widthY)-1 downto 0));
  end component;

  component AddMulPPGenSgn
    generic (widthX : positive;
	     widthY : positive);
    port (XS, XC : in std_logic_vector(widthX-1 downto 0);
	  Y : in std_logic_vector(widthY-1 downto 0);
	  PP : out std_logic_vector((widthX+1)*(widthX+widthY)-1 downto 0));
  end component;

  component SqrPPGenUns
    generic (width : positive);
    port (X : in std_logic_vector(width-1 downto 0);
	  PP : out std_logic_vector((width/2+1)*2*width-1 downto 0));
  end component;

  component SqrPPGenSgn
    generic (width : positive);
    port (X : in std_logic_vector(width-1 downto 0);
	  PP : out std_logic_vector((width/2+1)*2*width-1 downto 0));
  end component;


  -- compass compile_off
  component Decode
    generic (width : positive);
    port (A : in std_logic_vector(log2ceil(width)-1 downto 0);
	  Z : out std_logic_vector(width-1 downto 0));
  end component;

  component Encode
    generic (width : positive);
    port (A : in std_logic_vector(width-1 downto 0);
	  Z : out std_logic_vector(log2ceil(width)-1 downto 0));
  end component;
  -- compass compile_on

  
  component RedAnd
    generic (width : positive);
    port (A : in std_logic_vector(width-1 downto 0);
	  Z : out std_logic);
  end component;

  component RedOr
    generic (width : positive);
    port (A : in std_logic_vector(width-1 downto 0);
	  Z : out std_logic);
  end component;

  component RedXor
    generic (width : positive);
    port (A : in std_logic_vector(width-1 downto 0);
	  Z : out std_logic);
  end component;


  component Reg
    generic (width : positive);
    port (CLK : in std_logic;
	  RST : in std_logic;
          D : in std_logic_vector(width-1 downto 0);
          Q : out std_logic_vector(width-1 downto 0));
  end component;

  component FullAdder
    port (A, B, CI : in std_logic;
	  S, CO : out std_logic);
  end component;

  component ad01d1
    port (A, B, CI : in std_logic;
	  S, CO : out std_logic);
  end component;

end arith_lib;

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