decode.vhd

Cadence的VHDL运算库包

-------------------------------------------------------------------------------
-- Title       : Decoder
-- Project     : VHDL Library of Arithmetic Units
-------------------------------------------------------------------------------
-- File        : Decode.vhd
-- Author      : Reto Zimmermann  <[e-mail]>
-- Company     : Integrated Systems Laboratory, ETH Zurich
-- Date        : 1998/01/09
-------------------------------------------------------------------------------
-- Copyright (c) 1998 Integrated Systems Laboratory, ETH Zurich
-------------------------------------------------------------------------------
-- Description :
-- Decodes a binary number into a vector with a '1' at the according position.
-- Examples: A = "101" -> Z = "00100000".
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
library synergy;  use synergy.signed_arith.all;
library arith_lib;
use arith_lib.arith_lib.all;
use arith_lib.arith_utils.all;

-------------------------------------------------------------------------------

entity Decode is

  generic (width : positive := 8);  	-- word width

  port (A : in std_logic_vector(log2ceil(width)-1 downto 0);  -- encoded input
	Z : out std_logic_vector(width-1 downto 0));  -- output vector

end Decode;

-------------------------------------------------------------------------------

architecture Behavioral of Decode is

  signal Aint : integer;  -- integer
  signal Zint : integer;  -- integer

begin

  -- type conversion: std_logic_vector -> integer
  Aint <= conv_integer(unsigned(A));

  -- decoding
  Zint <= 2**Aint;

  -- type conversion: integer -> std_logic_vector
  Z <= std_logic_vector(conv_unsigned(Zint, width));

end Behavioral;

-------------------------------------------------------------------------------

architecture Structural of Decode is
  
  signal Aint : integer;  -- integer

begin

  -- type conversion: std_logic_vector -> integer
  Aint <= conv_integer(unsigned(A));

  -- decoding
  dec : for i in 0 to width-1 generate
    Z(i) <= '1' when Aint = i else '0';
  end generate dec;

end Structural;

-------------------------------------------------------------------------------