log2.vhd

Cadence的VHDL运算库包

-------------------------------------------------------------------------------
-- Title       : Integer logarithm
-- Project     : VHDL Library of Arithmetic Units
-------------------------------------------------------------------------------
-- File        : Log2.vhd
-- Author      : Reto Zimmermann  <[e-mail]>
-- Company     : Integrated Systems Laboratory, ETH Zurich
-- Date        : 1998/01/11
-------------------------------------------------------------------------------
-- Copyright (c) 1998 Integrated Systems Laboratory, ETH Zurich
-------------------------------------------------------------------------------
-- Description :
-- Computes integer logarithm to base 2 (Z = floor(log A)).
-- Example: A = "00010110" -> Z = "100".
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
library synergy;  use synergy.signed_arith.all;
library arith_lib;
use arith_lib.arith_lib.all;
use arith_lib.arith_utils.all;

-------------------------------------------------------------------------------

entity Log2 is

  generic (width : positive := 8;  	-- word width
	   speed : speedType := fast);  -- performance parameter

  port (A : in std_logic_vector(width-1 downto 0);  -- operand
	Z : out std_logic_vector(log2ceil(width)-1 downto 0)); -- result

end Log2;

-------------------------------------------------------------------------------

architecture Behavioral of Log2 is

begin

  -- compute integer logarithm
  log : process (A)
    variable zv : unsigned(log2ceil(width)-1 downto 0);
  begin
    zv := (others => '0');
    for i in 0 to width-1 loop
      if A(i) = '1' then
	zv := conv_unsigned(i, log2ceil(width));
      end if;
    end loop;
    Z <= std_logic_vector(zv);
  end process log;

end Behavioral;

-------------------------------------------------------------------------------

architecture Structural of Log2 is

  signal ZT : std_logic_vector(width-1 downto 0);  -- temp.

begin

  -- leading zero detection (i.e. most significant '1')
  loz : LeadZeroDet
    generic map (width, speed)
    port map (A, ZT);

  -- binary encode
  enc : Encode
    generic map (width)
    port map (ZT, Z);

end Structural;

-------------------------------------------------------------------------------