cntslice.vhd

Cadence的VHDL运算库包

-------------------------------------------------------------------------------
-- Title       : Slice for (m,k)-counter
-- Project     : VHDL Library of Arithmetic Units
-------------------------------------------------------------------------------
-- File        : CntSlice.vhd
-- Author      : Reto Zimmermann  <[e-mail]>
-- Company     : Integrated Systems Laboratory, ETH Zurich
-- Date        : 1997/11/16
-------------------------------------------------------------------------------
-- Copyright (c) 1998 Integrated Systems Laboratory, ETH Zurich
-------------------------------------------------------------------------------
-- Description :
-- Composed of full-adders arranged in linear or tree structure. Used as slice
-- for building (m,k)-counters. Forwards carries to next higher slice.
-- Condition: m > 3.
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
library arith_lib;
use arith_lib.arith_lib.all;

-------------------------------------------------------------------------------

entity CntSlice is

  generic (depth : positive := 4;	-- number of input bits
	   speed : speedType := fast);  -- performance parameter

  port (A : in std_logic_vector(depth-1 downto 0);  -- input bits
	S : out std_logic;  		-- sum out
	CO : out std_logic_vector(depth/2-1 downto 0));  -- carries out

end CntSlice;

-------------------------------------------------------------------------------

architecture Structural of CntSlice is

  constant noFA : positive := depth / 2;  -- number of used full-adders
  constant depthOdd : positive := depth + (depth+1) mod 2;  -- next higher odd
  signal F : std_logic_vector(3*noFA downto 0);	 -- FIFO vector of int. signals


begin

  -- put input bits to beginning of FIFO vector
  F(depth-1 downto 0) <= A;
  -- add a zero if even number of input bits
  even : if depth < depthOdd generate
    F(depthOdd-1) <= '0';
  end generate even;

  -- counter with linear structure
  slowCnt : if speed = slow generate

    -- first full-adder
    fa0 : FullAdder
      port map (F(0), F(1), F(2), F(depthOdd), CO(0));

    -- linear arrangement of full-adders
    linear : for i in 1 to noFA-1 generate
      fa : FullAdder
	port map (F(i*2+1), F(i*2+2), F(depthOdd+i-1), F(depthOdd+i), CO(i));
    end generate linear;

  end generate slowCnt;

  -- counter with tree structure
  fastCnt : if speed /= slow generate

    -- tree arrangement of full-adders
    tree : for i in 0 to noFA-1 generate
      fa : FullAdder
	port map (F(i*3), F(i*3+1), F(i*3+2), F(depthOdd+i), CO(i));
    end generate tree;

  end generate fastCnt;

    -- sum out
    S <= F(3*noFA);
    
end Structural;

-------------------------------------------------------------------------------