mulcsvuns.vhd

Cadence的VHDL运算库包

-------------------------------------------------------------------------------
-- Title       : Unsigned carry-save multiplier
-- Project     : VHDL Library of Arithmetic Units
-------------------------------------------------------------------------------
-- File        : MulCsvUns.vhd
-- Author      : Reto Zimmermann  <[e-mail]>
-- Company     : Integrated Systems Laboratory, ETH Zurich
-- Date        : 1998/01/19
-------------------------------------------------------------------------------
-- Copyright (c) 1998 Integrated Systems Laboratory, ETH Zurich
-------------------------------------------------------------------------------
-- Description :
-- Multiplier for unsigned numbers with one input operand and the
-- result in carry-save number representation (Brown). First adds two
-- numbers, then multiplies the result with the multiplicand without
-- performing final addition. Result is only valid if sum of
-- carry-save input operands does not overflow.
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
library synergy;  use synergy.signed_arith.all;
library arith_lib;
use arith_lib.arith_lib.all;

-------------------------------------------------------------------------------

entity MulCsvUns is

  generic (widthX : positive := 8;     -- word width of XS, XC (<= widthY)
	   widthY : positive := 8;     -- word width of Y
	   speed : speedType := fast);  -- performance parameter

  port (XS, XC : in std_logic_vector(widthX-1 downto 0);  -- multipliers
	Y : in std_logic_vector(widthY-1 downto 0);  -- multiplicand
        PS, PC : out std_logic_vector(widthX+widthY-1 downto 0));  -- product

end MulCsvUns;

-------------------------------------------------------------------------------

architecture Behavioral of MulCsvUns is

  signal XSuns, XCuns : unsigned(widthX-1 downto 0);  -- unsigned
  signal Yuns : unsigned(widthY-1 downto 0);  -- unsigned
  signal PSuns : unsigned(widthX+widthY-1 downto 0);  -- unsigned

begin

  -- type conversion: std_logic_vector -> unsigned
  XSuns <= unsigned(XS);
  XCuns <= unsigned(XC);
  Yuns <= unsigned(Y);

  -- addition and multiplication
  PSuns <= (XSuns + XCuns) * Yuns;

  -- type conversion: unsigned -> std_logic_vector
  PS <= std_logic_vector(PSuns);
  PC <= (others => '0');

end Behavioral;

-------------------------------------------------------------------------------

architecture Structural of MulCsvUns is 

						-- partial products
  signal PP : std_logic_vector(widthX*(widthX+widthY)-1 downto 0);
						-- intermediate sum/carry bits
  signal ST, CT : std_logic_vector(widthX+widthY-1 downto 0); 

begin

  -- generation of partial products
  ppGen : AddMulPPGenUns
    generic map (widthX, widthY)
    port map (XS, XC, Y, PP);

  -- carry-save addition of partial products
  csvAdd : AddMopCsv
    generic map (widthX+widthY, widthX, speed)
    port map (PP, PS, PC);

end Structural;

-------------------------------------------------------------------------------