addmod2nm1s0.vhd

来自「Cadence的VHDL运算库包」· VHDL 代码 · 共 90 行

-------------------------------------------------------------------------------
-- Title       : Parallel-prefix adder modulo (2^n - 1) (single zero repres.)
-- Project     : VHDL Library of Arithmetic Units
-------------------------------------------------------------------------------
-- File        : AddMod2Nm1s0.vhd
-- Author      : Reto Zimmermann  <[e-mail]>
-- Company     : Integrated Systems Laboratory, ETH Zurich
-- Date        : 1997/11/04
-------------------------------------------------------------------------------
-- Copyright (c) 1998 Integrated Systems Laboratory, ETH Zurich
-------------------------------------------------------------------------------
-- Description :
-- Binary adder modulo (2^n - 1) with single zero representation
-- (1's complement adder) using end-around carry parallel-prefix structure
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
library synergy;  use synergy.signed_arith.all;
library arith_lib;
use arith_lib.arith_lib.all;

-------------------------------------------------------------------------------

entity AddMod2Nm1s0 is

  generic (width : positive := 8;  	-- word width
           speed : speedType := fast);  -- performance parameter

  port (A, B : in std_logic_vector(width-1 downto 0);  -- operands
        S : out std_logic_vector(width-1 downto 0));  -- sum

end AddMod2Nm1s0;

-------------------------------------------------------------------------------

architecture Behavioral of AddMod2Nm1s0 is

  signal Auns, Buns, Suns, Tuns : unsigned(width downto 0);  -- unsigned
  constant modulus : unsigned(width downto 0)
      := conv_unsigned(2**width-1, width+1);  -- 2^n - 1

begin

  -- type conversion: std_logic_vector -> unsigned
  Auns <= conv_unsigned(A, width+1);
  Buns <= conv_unsigned(B, width+1);

  -- addition modulo (2^n - 1)
  Tuns <= Auns + Buns;
  Suns <= Tuns when Tuns < modulus else
          Tuns - modulus;

  -- type conversion: unsigned -> std_logic_vector
  S <= std_logic_vector(Suns(width-1 downto 0));

end Behavioral;

-------------------------------------------------------------------------------

architecture Structural of AddMod2Nm1s0 is 

  signal GI, PI : std_logic_vector(width-1 downto 0);  -- prefix gen./prop. in
  signal GO, PO : std_logic_vector(width-1 downto 0);  -- prefix gen./prop. out
  signal PT : std_logic_vector(width-1 downto 0);  -- adder propagate temp
  signal CI, CO : std_logic;  		-- end-around carries

begin

  -- calculate prefix input generate/propagate signals
  GI <= A and B;
  PI <= A or B;
  -- calculate adder propagate signals (PT = A xor B)
  PT <= not GI and PI;

  -- calculate prefix output generate/propagate signals with end-around carries
  prefix : PrefixAndOrCendaround
    generic map (width, speed)
    port map (GI, PI, CI, GO, PO, CO);

  -- end-around carry for addition modulo (2^n - 1), single zero repres.
  CI <= CO or PO(width-1);

  -- calculate sum bits
  S <= PT xor GO(width-2 downto 0) & CI;

end Structural;

-------------------------------------------------------------------------------