sqrtarruns.vhd

Cadence的VHDL运算库包

-------------------------------------------------------------------------------
-- Title       : Unsigned array square-root extractor
-- Project     : VHDL Library of Arithmetic Units
-------------------------------------------------------------------------------
-- File        : SqrtArrUns.vhd
-- Author      : Reto Zimmermann  <[e-mail]>
-- Company     : Integrated Systems Laboratory, ETH Zurich
-- Date        : 1997/12/05
-------------------------------------------------------------------------------
-- Copyright (c) 1998 Integrated Systems Laboratory, ETH Zurich
-------------------------------------------------------------------------------
-- Description :
-- Restoring array square-root extractor for unsigned numbers.
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
library synergy;  use synergy.signed_arith.all;
library arith_lib;
use arith_lib.arith_lib.all;

-------------------------------------------------------------------------------

entity SqrtArrUns is

  generic (widthX : positive := 8);	-- word width of X

  port (X : in std_logic_vector(widthX-1 downto 0);  -- operand
        Q : out std_logic_vector((widthX+1)/2-1 downto 0);  -- square root
        R : out std_logic_vector((widthX+1)/2-1 downto 0));  -- remainder

end SqrtArrUns;

-------------------------------------------------------------------------------

architecture Behavioral of SqrtArrUns is

  signal Xuns : unsigned(widthX-1 downto 0);  -- unsigned
  signal Quns : unsigned((widthX+1)/2-1 downto 0);  -- unsigned
  signal Runs : unsigned(2*((widthX+1)/2)-1 downto 0);  -- unsigned

begin

  -- type conversion: std_logic_vector -> unsigned
  Xuns <= unsigned(X);

  -- square root extraction
  sqrt : process (Xuns)
    variable qv : unsigned((widthX+1)/2 downto 0);
  begin
    qv := (others => '0');
    while (qv+1)*(qv+1) <= Xuns loop
      qv := qv + 1;
    end loop;
    Quns <= qv((widthX+1)/2-1 downto 0);
  end process sqrt;

  -- calculate remainder
  Runs <= Xuns - Quns*Quns;

  -- type conversion: unsigned -> std_logic_vector
  Q <= std_logic_vector(Quns((widthX+1)/2-1 downto 0));
  R <= std_logic_vector(Runs((widthX+1)/2-1 downto 0));

end Behavioral;

-------------------------------------------------------------------------------

architecture Structural of SqrtArrUns is

  constant widthQ : positive := (widthX+1)/2;  -- word width of Q

  signal XT : std_logic_vector(widthX downto 0);  -- extended operand
  signal QT : std_logic_vector(widthQ-1 downto 0);  -- temp. quotient
  signal QTI : std_logic_vector(widthQ*(widthQ+2)-1 downto 0);  -- quotients
  signal ST : std_logic_vector(widthQ*(widthQ+2)-1 downto 0);  -- sums
  signal RT : std_logic_vector((widthQ+1)*(widthQ+3)-1 downto 0); -- remainders
  signal CT : std_logic_vector(widthQ*(widthQ+3)-1 downto 0);  -- carries

begin

  -- extend operand X
  XT <= '0' & X;
  
  -- first partial remainder is operand X
  RT(widthQ*(widthQ+3)+widthQ+1 downto widthQ*(widthQ+3)+1) <=
    '0' & XT(2*widthQ-1 downto widthQ);

  -- process one row for each quotient bit
  row : for k in widthQ-1 downto 0 generate

    -- carry-in = '1' for subtraction
    CT(k*(widthQ+3)) <= '1';
    -- attach next operand bit to current remainder
    RT((k+1)*(widthQ+3)) <= XT(k);
    
    -- form current partial quotient (inverted)
    partQuot : process (QT)
      variable qtv : std_logic_vector(widthQ+1 downto 0);
    begin
      qtv := (others => '0');
      if k /= widthQ-1 then
	qtv(widthQ+1 downto k) := '0' & QT(widthQ-1 downto k+1) & '0' & '1';
      else
	qtv(widthQ+1 downto k) := '0' & '0' & '1';
      end if;
      QTI(k*(widthQ+2)+widthQ+1 downto k*(widthQ+2)) <= not qtv;
    end process partQuot;

    -- perform subtraction using ripple-carry adder
    -- (partial remainder - partial quotient)
    bits : for i in widthQ+1 downto 0 generate
      fa : FullAdder
	port map (QTI(k*(widthQ+2)+i), RT((k+1)*(widthQ+3)+i),
		  CT(k*(widthQ+3)+i),
		  ST(k*(widthQ+2)+i), CT(k*(widthQ+3)+i+1));
    end generate bits;

    -- if subtraction result is negative => quotient bit = '0'
    QT(k) <= CT(k*(widthQ+3)+widthQ+2);

    -- restore previous partial remainder if quotient bit = '0'
    RT(k*(widthQ+3)+widthQ+2 downto k*(widthQ+3)+1) <=
      RT((k+1)*(widthQ+3)+widthQ+1 downto (k+1)*(widthQ+3))
							when QT(k) = '0' else
      ST(k*(widthQ+2)+widthQ+1 downto k*(widthQ+2));

  end generate row;

  Q <= QT;
  
  -- last partial remainder is division remainder
  R <= RT(widthQ downto 1);

end Structural;

-------------------------------------------------------------------------------