divarrsgn.vhd

Cadence的VHDL运算库包

-------------------------------------------------------------------------------
-- Title       : Signed array divider
-- Project     : VHDL Library of Arithmetic Units
-------------------------------------------------------------------------------
-- File        : DivArrSgn.vhd
-- Author      : Reto Zimmermann  <[e-mail]>
-- Company     : Integrated Systems Laboratory, ETH Zurich
-- Date        : 1997/12/03
-------------------------------------------------------------------------------
-- Copyright (c) 1998 Integrated Systems Laboratory, ETH Zurich
-------------------------------------------------------------------------------
-- Description :
-- Restoring array divider for signed numbers. The divisor must be normalized
-- (i.e. Y(widthY-1) = '1')
--
-- NOTE: not completed. very difficult to implement for signed numbers.
-- problem with zero result if result otherwise negative
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
library synergy;  use synergy.signed_arith.all;
library arith_lib;
use arith_lib.arith_lib.all;

-------------------------------------------------------------------------------

entity DivArrSgn is

  generic (widthX : positive := 16;	-- word width of X
	   widthY : positive := 8);	-- word width of Y

  port (X : in std_logic_vector(widthX-1 downto 0);  -- dividend
	Y : in std_logic_vector(widthY-1 downto 0);  -- divisor, normalized
        Q : out std_logic_vector(widthX-widthY downto 0);  -- quotient
        R : out std_logic_vector(widthY-1 downto 0));  -- remainder

end DivArrSgn;

-------------------------------------------------------------------------------

architecture Behavioral of DivArrSgn is

  signal Xuns : signed(widthX-1 downto 0);  -- signed
  signal Yuns : signed(widthY-1 downto 0);  -- signed
  signal Quns : signed(widthX-1 downto 0);  -- signed
  signal Runs : signed(widthY-1 downto 0);  -- signed

begin

  -- type conversion: std_logic_vector -> signed
  Xuns <= signed(X);
  Yuns <= signed(Y);

  -- division => quotient
  Quns <= Xuns / Yuns;

  -- modulo => remainder
  Runs <= Xuns mod Yuns;

  -- type conversion: signed -> std_logic_vector
  Q <= std_logic_vector(Quns(widthX-widthY downto 0));
  R <= std_logic_vector(Runs);

end Behavioral;

-------------------------------------------------------------------------------

architecture Structural of DivArrSgn is

  constant widthQ : positive := widthX-widthY+1;  -- word width of Q

  signal YI : std_logic_vector(widthY downto 0);  -- inverted Y
  signal ST : std_logic_vector(widthQ*(widthY+1)-1 downto 0);  -- sums
  signal QT : std_logic_vector(widthQ-1 downto 0);  -- sums
  signal RT : std_logic_vector((widthQ+1)*(widthY+2)-1 downto 0); -- remainders
  signal CT : std_logic_vector(widthQ*(widthY+2)-1 downto 0);  -- carries

begin

  -- invert divisor Y for subtraction
  YI <= not Y(widthY-1) & not Y;
  -- first partial remainder is dividend X
  RT(widthQ*(widthY+2)+widthY downto widthQ*(widthY+2)+1) <=
    X(widthX-1) & X(widthX-1 downto widthX-widthY+1);

  -- process one row for each quotient bit
  row : for k in widthQ-1 downto 0 generate

    -- carry-in = '1' for subtraction
    CT(k*(widthY+2)) <= '1';
    -- attach next dividend bit to current remainder
    RT((k+1)*(widthY+2)) <= X(k);

    -- perform subtraction using ripple-carry adder
    -- (currend partial remainder - divisor)
    bits : for i in widthY downto 0 generate
      fa : FullAdder
	port map (YI(i), RT((k+1)*(widthY+2)+i), CT(k*(widthY+2)+i),
		  ST(k*(widthY+1)+i), CT(k*(widthY+2)+i+1));
    end generate bits;

    -- if subtraction result is negative => quotient bit = '0'
    QT(k) <= CT(k*(widthY+2)+widthY+1);

    -- restore previous partial remainder is quotient bit = '0'
    RT(k*(widthY+2)+widthY+1 downto k*(widthY+2)+1) <=
      RT((k+1)*(widthY+2)+widthY downto (k+1)*(widthY+2))
						when QT(k) = '0' else
      ST(k*(widthY+1)+widthY downto k*(widthY+1));

  end generate row;

  Q <= QT;
  -- last partial remainder is division remainder
  R <= RT(widthY downto 1);

end Structural;

-------------------------------------------------------------------------------