leadonedet.vhd

Cadence的VHDL运算库包

-------------------------------------------------------------------------------
-- Title       : Leading-ones detector (LOD)
-- Project     : VHDL Library of Arithmetic Units
-------------------------------------------------------------------------------
-- File        : LeadOneDet.vhd
-- Author      : Reto Zimmermann  <[e-mail]>
-- Company     : Integrated Systems Laboratory, ETH Zurich
-- Date        : 1997/12/29
-------------------------------------------------------------------------------
-- Copyright (c) 1998 Integrated Systems Laboratory, ETH Zurich
-------------------------------------------------------------------------------
-- Description :
-- Detection of leading ones. Output vector indicates position of the first
-- '0' (starting at MSB).
-- Example: A = "111010" -> Z = "000100".
-- Use the `Encode' component for encoding the output (-> Z = "010").
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
library arith_lib;
use arith_lib.arith_lib.all;

-------------------------------------------------------------------------------

entity LeadOneDet is

  generic (width : positive := 8;  	-- word width
	   speed : speedType := fast);  -- performance parameter

  port (A : in std_logic_vector(width-1 downto 0);  -- operand
	Z : out std_logic_vector(width-1 downto 0));  -- LOD output

end LeadOneDet;

-------------------------------------------------------------------------------

architecture Behavioral of LeadOneDet is

begin

  -- leading-ones detection
  lod : process (A)
    variable zv : std_logic_vector(width-1 downto 0);
  begin
    zv := (others => '0');
    for i in width-1 downto 0 loop
      if A(i) = '0' then
	zv(i) := '1';
	exit;
      end if;
    end loop;
    Z <= zv;
  end process lod;

end Behavioral;

-------------------------------------------------------------------------------

architecture Structural of LeadOneDet is

  signal PI, PO : std_logic_vector(width-1 downto 0);  -- prefix prop. in/out
  signal PIT, POT : std_logic_vector(width-1 downto 0);  -- temp.

begin

  -- calculate prefix propagate in signals
  PI <= A;
  
  -- reverse bit order of PI
  revPI : for i in width-1 downto 0 generate
    PIT(i) <= PI(width-i-1);
  end generate revPI;

  -- solve reverse prefix problem for leading-ones detection
  -- (example: "111010" -> "111100")
  prefix : PrefixAnd
    generic map (width, speed)
    port map (PIT, POT);

  -- reverse bit order of PO
  revPO : for i in width-1 downto 0 generate
    PO(i) <= POT(width-i-1);
  end generate revPO;

  -- code output: only bit indicating position of first '0' is '1'
  -- (example: "111010" -> "000100")
  Z(width-1) <= not A(width-1);
  Z(width-2 downto 0) <= PO(width-1 downto 1) and not A(width-2 downto 0);

end Structural;

-------------------------------------------------------------------------------