addcsv.vhd

Cadence的VHDL运算库包

-------------------------------------------------------------------------------
-- Title       : Carry-save adder (3 operands)
-- Project     : VHDL Library of Arithmetic Units
-------------------------------------------------------------------------------
-- File        : AddCsv.vhd
-- Author      : Reto Zimmermann  <[e-mail]>
-- Company     : Integrated Systems Laboratory, ETH Zurich
-- Date        : 1997/11/12
-------------------------------------------------------------------------------
-- Copyright (c) 1998 Integrated Systems Laboratory, ETH Zurich
-------------------------------------------------------------------------------
-- Description :
-- Three-operand carry-save adder using full-adders.
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
library synergy;  use synergy.signed_arith.all;
library arith_lib;
use arith_lib.arith_lib.all;

-------------------------------------------------------------------------------

entity AddCsv is

  generic (width : positive := 8);	-- word width

  port (A1, A2, A3 : in std_logic_vector(width-1 downto 0);  -- operands
	S, C : out std_logic_vector(width-1 downto 0));  -- sum / carry vector

end AddCsv;

-------------------------------------------------------------------------------

architecture Behavioral of AddCsv is

  signal A1uns, A2uns, A3uns : unsigned(width-1 downto 0);  -- unsigned
  signal Suns : unsigned(width-1 downto 0);  -- unsigned

begin

  -- type conversion: std_logic_vector -> unsigned
  A1uns <= unsigned(A1);
  A2uns <= unsigned(A2);
  A3uns <= unsigned(A3);

  -- three-operand addition
  Suns <= A1uns + A2uns + A3uns;

  -- type conversion: unsigned -> std_logic_vector
  S <= std_logic_vector(Suns);
  C <= (others => '0');

end Behavioral;

-------------------------------------------------------------------------------

architecture Structural of AddCsv is 

  signal CT : std_logic_vector(width-1 downto 0);  -- unshifted output carries

begin

  -- carry-save addition using full-adders
  bits : for i in 0 to width-1 generate
    fa : FullAdder
      port map (A1(i), A2(i), A3(i), S(i), CT(i));
  end generate bits;

  -- rotate output carries by one position
  C <= CT(width-2 downto 0) & '0'; 

end Structural;

-------------------------------------------------------------------------------