allonedet.vhd

Cadence的VHDL运算库包

-------------------------------------------------------------------------------
-- Title       : All-ones detector
-- Project     : VHDL Library of Arithmetic Units
-------------------------------------------------------------------------------
-- File        : AllOneDet.vhd
-- Author      : Reto Zimmermann  <[e-mail]>
-- Company     : Integrated Systems Laboratory, ETH Zurich
-- Date        : 1997/12/29
-------------------------------------------------------------------------------
-- Copyright (c) 1998 Integrated Systems Laboratory, ETH Zurich
-------------------------------------------------------------------------------
-- Description :
-- Detection of the all-ones vector.
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
library arith_lib;
use arith_lib.arith_lib.all;

-------------------------------------------------------------------------------

entity AllOneDet is

  generic (width : positive := 8);  	-- word width

  port (A : in std_logic_vector(width-1 downto 0);  -- operand
	Z : out std_logic);		-- all-ones flag

end AllOneDet;

-------------------------------------------------------------------------------

architecture Behavioral of AllOneDet is

  signal Ones : std_logic_vector(width-1 downto 0);  -- ones vector

begin

  -- initialization of ones vector
  Ones <= (others => '1');

  -- all-ones detection
  Z <= '1' when A = Ones else '0';

end Behavioral;

-------------------------------------------------------------------------------

architecture Structural of AllOneDet is

  signal ZT : std_logic_vector(width-1 downto 0);  -- temp.

begin

  -- all-ones detection
  zeroFlag : RedAnd
    generic map (width)
    port map (A, Z);

end Structural;

-------------------------------------------------------------------------------