addmulppgenuns.vhd

来自「Cadence的VHDL运算库包」· VHDL 代码 · 共 77 行

-------------------------------------------------------------------------------
-- Title       : Partial-product generator for unsigned adder-multiplier
-- Project     : VHDL Library of Arithmetic Units
-------------------------------------------------------------------------------
-- File        : AddMulPPGenUns.vhd
-- Author      : Reto Zimmermann  <[e-mail]>
-- Company     : Integrated Systems Laboratory, ETH Zurich
-- Date        : 1997/11/19
-------------------------------------------------------------------------------
-- Copyright (c) 1998 Integrated Systems Laboratory, ETH Zurich
-------------------------------------------------------------------------------
-- Description :
-- Partial-product generator for unsigned addermultiplier (Braun) (i.e.
-- multiplier is sum of two input operands).
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
library arith_lib;
use arith_lib.arith_lib.all;

-------------------------------------------------------------------------------

entity AddMulPPGenUns is

  generic (widthX : positive := 8;	-- word width of XS, XC
	   widthY : positive := 8);	-- word width of Y

  port (XS, XC : in std_logic_vector(widthX-1 downto 0);  -- multipliers
	Y : in std_logic_vector(widthY-1 downto 0);  -- multiplicand
						     -- partial products
        PP : out std_logic_vector(widthX*(widthX+widthY)-1 downto 0));

end AddMulPPGenUns;

-------------------------------------------------------------------------------

architecture Structural of AddMulPPGenUns is 

  constant widthP : positive := widthX+widthY;  -- width of single part. prod.

  signal M1, M2 : std_logic_vector(widthX-1 downto 0);  -- recoded multiplier
  signal YT : std_logic_vector(widthY+1 downto 0);  -- expanded Y

begin

  -- recode multiplier
  M1 <= XS xor XC;
  M2 <= XS and XC;

  -- expand Y (used for term 2y)
  YT <= '0' & Y(widthY-1 downto 0) & '0';

  ppGen : process (M1, M2, YT)
    variable ppt : std_logic_vector(widthX*widthP-1 downto 0);
  begin

    -- defaults
    ppt := (others => '0');

    -- partial products (xs(i)+xc(i))y(k):
    --   if M1 = '1' then y(i)
    --   if M2 = '1' then 2y(i)
    for i in 0 to widthX-1 loop
      for k in 0 to widthY loop
	ppt(i*widthP+i+k) := (M1(i) and YT(k+1)) or (M2(i) and YT(k));
      end loop;
    end loop;

    PP <= ppt;

  end process ppGen;

end Structural;

-------------------------------------------------------------------------------