leadsigndet.vhd

Cadence的VHDL运算库包

-------------------------------------------------------------------------------
-- Title       : Leading-signs detector (LSD)
-- Project     : VHDL Library of Arithmetic Units
-------------------------------------------------------------------------------
-- File        : LeadSignDet.vhd
-- Author      : Reto Zimmermann  <[e-mail]>
-- Company     : Integrated Systems Laboratory, ETH Zurich
-- Date        : 1997/12/29
-------------------------------------------------------------------------------
-- Copyright (c) 1998 Integrated Systems Laboratory, ETH Zurich
-------------------------------------------------------------------------------
-- Description :
-- Detection of leading signs (i.e. leading-zeroes/ones detection for signed
-- numbers). Output vector indicates position of the first bit which differs
-- from the sign (starting at MSB).
-- Examples: A = "000101" -> Z = "000100", A = "111010" -> Z = "000100".
-- Use the `Encode' component for encoding the output (-> Z = "010").
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
library arith_lib;
use arith_lib.arith_lib.all;

-------------------------------------------------------------------------------

entity LeadSignDet is

  generic (width : positive := 8;  	-- word width
	   speed : speedType := fast);  -- performance parameter

  port (A : in std_logic_vector(width-1 downto 0);  -- operand
	Z : out std_logic_vector(width-1 downto 0));  -- LSD output

end LeadSignDet;

-------------------------------------------------------------------------------

architecture Behavioral of LeadSignDet is

begin

  -- leading-signs detection
  lsd : process (A)
    variable zv : std_logic_vector(width-1 downto 0);
  begin
    zv := (others => '0');
    for i in width-2 downto 0 loop
      if A(i) /= A(width-1) then
	zv(i) := '1';
	exit;
      end if;
    end loop;
    Z <= zv;
  end process lsd;

end Behavioral;

-------------------------------------------------------------------------------

architecture Structural of LeadSignDet is

  signal PI, PO : std_logic_vector(width-2 downto 0);  -- prefix prop. in/out
  signal PIT, POT : std_logic_vector(width-2 downto 0);  -- temp.

begin

  -- calculate prefix propagate in signals (depends on sign)
  pre : for i in width-2 downto 0 generate
    PI(i) <= not (A(width-1) xor A(i));
  end generate pre;
  
  -- reverse bit order of PI
  revPI : for i in width-2 downto 0 generate
    PIT(i) <= PI(width-i-2);
  end generate revPI;

  -- solve reverse prefix problem for leading-signs detection
  -- (example: "000101" -> "111100")
  prefix : PrefixAnd
    generic map (width-1, speed)
    port map (PIT, POT);

  -- reverse bit order of PO
  revPO : for i in width-2 downto 0 generate
    PO(i) <= POT(width-i-2);
  end generate revPO;

  -- code output: only bit indicating position of first non-sign is '1'
  -- (example: "000101" -> "000100")
  Z(width-1) <= '0';
  Z(width-2) <= A(width-1) xor A(width-2);
  post : for i in width-3 downto 0 generate
    Z(i) <= PO(i+1) and (A(width-1) xor A(i));
  end generate post;

end Structural;

-------------------------------------------------------------------------------