addmop.vhd

Cadence的VHDL运算库包

-------------------------------------------------------------------------------
-- Title       : Multi-operand adder
-- Project     : VHDL Library of Arithmetic Units
-------------------------------------------------------------------------------
-- File        : AddMop.vhd
-- Author      : Reto Zimmermann  <[e-mail]>
-- Company     : Integrated Systems Laboratory, ETH Zurich
-- Date        : 1997/11/14
-------------------------------------------------------------------------------
-- Copyright (c) 1998 Integrated Systems Laboratory, ETH Zurich
-------------------------------------------------------------------------------
-- Description :
-- Multi-operand adder using carry-save adder /array/tree and
-- ripple-carry/parallel-prefix final adder.
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
library synergy;  use synergy.signed_arith.all;
library arith_lib;
use arith_lib.arith_lib.all;

-------------------------------------------------------------------------------

entity AddMop is

  generic (width : positive := 8;  	-- word width
	   depth : positive := 4;  	-- number of operands
	   speed : speedType := fast);  -- performance parameter

  port (A : in std_logic_vector(depth*width-1 downto 0);  -- operands
	S : out std_logic_vector(width-1 downto 0));  -- sum

end AddMop;

-------------------------------------------------------------------------------

architecture Behavioral of AddMop is

  signal Auns : unsigned(depth*width-1 downto 0);  -- unsigned
  signal Suns : unsigned(width-1 downto 0);  -- unsigned

begin

  -- type conversion: std_logic_vector -> unsigned
  Auns <= unsigned(A);

  -- multi-operand addition
  add : process (Auns)
    variable s : unsigned(width-1 downto 0);
  begin
    s := (others => '0');
    for i in 0 to depth-1 loop
      s := s + Auns((i+1)*width-1 downto i*width);
    end loop;
    Suns <= s;
  end process add;

  -- type conversion: unsigned -> std_logic_vector
  S <= std_logic_vector(Suns);

end Behavioral;

-------------------------------------------------------------------------------

architecture Structural of AddMop is 

  signal ST, CT : std_logic_vector(width-1 downto 0); -- interm. sum/carry bits

begin

  -- carry-save addition
  csvAdd : AddMopCsv
    generic map (width, depth, speed)
    port map (A, ST, CT);

  -- final carry-propagate addition
  finalAdd : Add
    generic map (width, speed)
    port map (ST, CT, S);

end Structural;

-------------------------------------------------------------------------------