sumzerodet.vhd

Cadence的VHDL运算库包

-------------------------------------------------------------------------------
-- Title       : Fast zero-sum detection
-- Project     : VHDL Library of Arithmetic Units
-------------------------------------------------------------------------------
-- File        : SumZeroDet.vhd
-- Author      : Reto Zimmermann  <[e-mail]>
-- Company     : Integrated Systems Laboratory, ETH Zurich
-- Date        : 1998/01/09
-------------------------------------------------------------------------------
-- Copyright (c) 1998 Integrated Systems Laboratory, ETH Zurich
-------------------------------------------------------------------------------
-- Description :
-- Detects an all-zeroes sum of an addition in constant time, i.e. without
-- waiting for the slow addition result (or without performing the addition).
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
library synergy;  use synergy.signed_arith.all;
library arith_lib;
use arith_lib.arith_lib.all;

-------------------------------------------------------------------------------

entity SumZeroDet is

  generic (width : positive := 8);  	-- word width

  port (A, B : in std_logic_vector(width-1 downto 0);  -- operands
        CI : in std_logic;  		-- carry in
	Z : out std_logic);		-- all-zeroes sum flag

end SumZeroDet;

-------------------------------------------------------------------------------

architecture Behavioral of SumZeroDet is

  signal Auns, Buns, CIuns : unsigned(width-1 downto 0);  -- unsigned

begin

  -- type conversion: std_logic_vector -> unsigned
  Auns <= unsigned(A);
  Buns <= unsigned(B);
  CIuns <= (0 => CI, others => '0');

  -- all-zeroes sum detection
  Z <= '1' when Auns + Buns + CIuns = 0 else '0';

end Behavioral;

-------------------------------------------------------------------------------

architecture Structural of SumZeroDet is

  signal ZT : std_logic_vector(width-1 downto 0);  -- temp.

begin

  -- zero flag for individual bits
  ZT(0) <= not ((A(0) xor B(0)) xor CI);
  zeroBit : for i in 1 to width-1 generate
    ZT(i) <= not ((A(i) xor B(i)) xor (A(i-1) or B(i-1)));
  end generate zeroBit;

  -- AND all bit zero flags
  zeroFlag : RedAnd
    generic map (width)
    port map (ZT, Z);

end Structural;

-------------------------------------------------------------------------------