gray2bin.vhd

Cadence的VHDL运算库包

-------------------------------------------------------------------------------
-- Title       : Gray-to-binary converter
-- Project     : VHDL Library of Arithmetic Units
-------------------------------------------------------------------------------
-- File        : Gray2Bin.vhd
-- Author      : Reto Zimmermann  <[e-mail]>
-- Company     : Integrated Systems Laboratory, ETH Zurich
-- Date        : 1997/12/28
-------------------------------------------------------------------------------
-- Copyright (c) 1998 Integrated Systems Laboratory, ETH Zurich
-------------------------------------------------------------------------------
-- Description :
-- Converts a number from Gray to binary representation. Corresponds to a
-- prefix problem in reversed bit order (compared to addition)
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
library arith_lib;
use arith_lib.arith_lib.all;

-------------------------------------------------------------------------------

entity Gray2Bin is

  generic (width : positive := 8;	-- word width
	   speed : speedType := fast);  -- performance parameter

  port (G : in std_logic_vector(width-1 downto 0);  -- Gray input
	B : out std_logic_vector(width-1 downto 0));  -- binary output

end Gray2Bin;

-------------------------------------------------------------------------------

architecture Behavioral of Gray2Bin is

  signal BT : std_logic_vector(width downto 0);  -- temp.

begin

  -- recursive description of Gray to binary conversion
  g2b : process (G)
    variable bv : std_logic_vector(width downto 0);
  begin
    bv(width) := '0';
    for i in width-1 downto 0 loop
      bv(i) := bv(i+1) xor G(i);
    end loop;
    
    B <= bv(width-1 downto 0);
  end process g2b;

end Behavioral;

-------------------------------------------------------------------------------

architecture Structural of Gray2Bin is

  signal BT, GT : std_logic_vector(width-1 downto 0);  -- temp.

begin

  -- reverse bit order of G
  revG : for i in width-1 downto 0 generate
    GT(i) <= G(width-i-1);
  end generate revG;

  -- convert Gray to binary using prefix XOR computation
  prefix : PrefixXor
    generic map (width, speed)
    port map (GT, BT);

  -- reverse bit order of B
  revB : for i in width-1 downto 0 generate
    B(i) <= BT(width-i-1);
  end generate revB;

end Structural;

-------------------------------------------------------------------------------