sqruns.vhd

Cadence的VHDL运算库包

-------------------------------------------------------------------------------
-- Title       : Unsigned squarer
-- Project     : VHDL Library of Arithmetic Units
-------------------------------------------------------------------------------
-- File        : SqrUns.vhd
-- Author      : Reto Zimmermann  <[e-mail]>
-- Company     : Integrated Systems Laboratory, ETH Zurich
-- Date        : 1997/11/14
-------------------------------------------------------------------------------
-- Copyright (c) 1998 Integrated Systems Laboratory, ETH Zurich
-------------------------------------------------------------------------------
-- Description :
-- Squarer for unsigned numbers using optimized partial-product generation,
-- carry-save adder and final adder.
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
library synergy;  use synergy.signed_arith.all;
library arith_lib;
use arith_lib.arith_lib.all;

-------------------------------------------------------------------------------

entity SqrUns is

  generic (width : positive := 8;	-- word width
	   speed : speedType := fast);  -- performance parameter

  port (X : in std_logic_vector(width-1 downto 0);  -- operand
        P : out std_logic_vector(2*width-1 downto 0));  -- product

end SqrUns;

-------------------------------------------------------------------------------

architecture Behavioral of SqrUns is

  signal Xuns : unsigned(width-1 downto 0);  -- unsigned
  signal Puns : unsigned(2*width-1 downto 0);  -- unsigned

begin

  -- type conversion: std_logic_vector -> unsigned
  Xuns <= unsigned(X);

  -- multiplication
  Puns <= Xuns * Xuns;

  -- type conversion: unsigned -> std_logic_vector
  P <= std_logic_vector(Puns);

end Behavioral;

-------------------------------------------------------------------------------

architecture Structural of SqrUns is 

						-- partial products
  signal PP : std_logic_vector((width/2+1)*2*width-1 downto 0);
						-- intermediate sum/carry bits
  signal ST, CT : std_logic_vector(2*width-1 downto 0); 

begin

  -- generation of partial products
  ppGen : SqrPPGenUns
    generic map (width)
    port map (X, PP);

  -- carry-save addition of partial products
  csvAdd : AddMopCsv
    generic map (2*width, width/2+1, speed)
    port map (PP, ST, CT);

  -- final carry-propagate addition
  cpAdd : Add
    generic map (2*width, speed)
    port map (ST, CT, P);

end Structural;

-------------------------------------------------------------------------------