incc.vhd

Cadence的VHDL运算库包

-------------------------------------------------------------------------------
-- Title       : Parallel-prefix incrementer with carry-in, carry-out
-- Project     : VHDL Library of Arithmetic Units
-------------------------------------------------------------------------------
-- File        : IncC.vhd
-- Author      : Reto Zimmermann  <[e-mail]>
-- Company     : Integrated Systems Laboratory, ETH Zurich
-- Date        : 1997/11/04
-------------------------------------------------------------------------------
-- Copyright (c) 1998 Integrated Systems Laboratory, ETH Zurich
-------------------------------------------------------------------------------
-- Description :
-- Incrementer using parallel-prefix propagate-lookahead logic with:
--   - carry-in (CI)
--   - carry-out (CO)
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
library synergy;  use synergy.signed_arith.all;
library arith_lib;
use arith_lib.arith_lib.all;

-------------------------------------------------------------------------------

entity IncC is

  generic (width : positive := 8;  	-- word width
	   speed : speedType := fast);  -- performance parameter

  port (A : in std_logic_vector(width-1 downto 0);  -- operand
        CI : in std_logic;  		-- carry in
	Z : out std_logic_vector(width-1 downto 0);  -- result
        CO : out std_logic);  		-- carry out

end IncC;

-------------------------------------------------------------------------------

architecture Behavioral of IncC is

  signal Auns, CIuns, Zuns : unsigned(width downto 0);  -- unsigned

begin

  -- type conversion: std_logic_vector -> unsigned
  Auns <= conv_unsigned(A, width+1);
  CIuns <= (0 => CI, others => '0');

  -- increment
  Zuns <= Auns + CIuns;

  -- type conversion: unsigned -> std_logic_vector
  Z <= std_logic_vector(Zuns(width-1 downto 0));
  CO <= Zuns(width);

end Behavioral;

-------------------------------------------------------------------------------

architecture Structural of IncC is 

  signal AI : std_logic_vector(width downto 0);  -- A inverted
  signal PO : std_logic_vector(width downto 0);  -- prefix propagate out

begin

  -- attach carry-in
  AI <= A & CI;
  
  -- calculate prefix output propagate signal
  prefix : PrefixAnd
    generic map (width+1, speed)
    port map (AI, PO);

  -- calculate result and carry-out bits
  Z <= A xor PO(width-1 downto 0);
  CO <= PO(width);

end Structural;

-------------------------------------------------------------------------------