addmod2np1.vhd

Cadence的VHDL运算库包

-------------------------------------------------------------------------------
-- Title       : Parallel-prefix adder modulo (2^n + 1)
-- Project     : VHDL Library of Arithmetic Units
-------------------------------------------------------------------------------
-- File        : AddMod2Np1.vhd
-- Author      : Reto Zimmermann  <[e-mail]>
-- Company     : Integrated Systems Laboratory, ETH Zurich
-- Date        : 1997/11/04
-------------------------------------------------------------------------------
-- Copyright (c) 1998 Integrated Systems Laboratory, ETH Zurich
-------------------------------------------------------------------------------
-- Description :
-- Binary adder modulo (2^n + 1) using end-around carry parallel-prefix
-- structure, diminished-one number representation
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
library synergy;  use synergy.signed_arith.all;
library arith_lib;
use arith_lib.arith_lib.all;

-------------------------------------------------------------------------------

entity AddMod2Np1 is

  generic (width : positive := 8;       -- word width
           speed : speedType := fast);  -- performance parameter

  port (A, B : in std_logic_vector(width-1 downto 0);  -- operands
        S : out std_logic_vector(width-1 downto 0));  -- sum

end AddMod2Np1;

-------------------------------------------------------------------------------

architecture Behavioral of AddMod2Np1 is

  signal Auns, Buns, Suns : unsigned(width+1 downto 0);  -- unsigned
  constant modulus : unsigned(width+1 downto 0)
    := conv_unsigned(2**width+1, width+2);  -- 2^n + 1

begin

  -- type conversion: std_logic_vector diminished-one -> unsigned (n+2 bits)
  Auns <= conv_unsigned(A, width+2) + 1;
  Buns <= conv_unsigned(B, width+2) + 1;

  -- addition modulo (2^n + 1)
  Suns <= (Auns + Buns) mod modulus;

  -- type conversion: unsigned -> std_logic_vector diminished-one
  S <=  std_logic_vector(conv_unsigned(0, width)) when Suns = 0 else
        std_logic_vector(Suns(width-1 downto 0) - 1);
  
end Behavioral;

-------------------------------------------------------------------------------

architecture Structural of AddMod2Np1 is 

  signal GI, PI : std_logic_vector(width-1 downto 0);  -- prefix gen./prop. in
  signal GO, PO : std_logic_vector(width-1 downto 0);  -- prefix gen./prop. out
  signal PT : std_logic_vector(width-1 downto 0);  -- adder propagate temp
  signal CI, CO : std_logic;  		-- end-around carries

begin

  -- calculate prefix input generate/propagate signals
  GI <= A and B;
  PI <= A or B;
  -- calculate adder propagate signals (P = A xor B)
  PT <= not GI and PI;

  -- calculate prefix output generate/propagate signals with end-around carries
  prefix : PrefixAndOrCendaround
    generic map (width, speed)
    port map (GI, PI, CI, GO, PO, CO);

  -- end-around carry for addition modulo (2^n + 1)
  CI <= not CO;

  -- calculate sum bits
  S <= PT xor GO(width-2 downto 0) & CI;

end Structural;

-------------------------------------------------------------------------------