dec.vhd

Cadence的VHDL运算库包

-------------------------------------------------------------------------------
-- Title       : Parallel-prefix decrementer
-- Project     : VHDL Library of Arithmetic Units
-------------------------------------------------------------------------------
-- File        : Dec.vhd
-- Author      : Reto Zimmermann  <[e-mail]>
-- Company     : Integrated Systems Laboratory, ETH Zurich
-- Date        : 1997/11/04
-------------------------------------------------------------------------------
-- Copyright (c) 1998 Integrated Systems Laboratory, ETH Zurich
-------------------------------------------------------------------------------
-- Description :
-- Decrementer using parallel-prefix propagate-lookahead logic.
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
library synergy;  use synergy.signed_arith.all;
library arith_lib;
use arith_lib.arith_lib.all;

-------------------------------------------------------------------------------

entity Dec is

  generic (width : positive := 8;  	-- word width
	   speed : speedType := fast);  -- performance parameter

  port (A : in std_logic_vector(width-1 downto 0);  -- operand
	Z : out std_logic_vector(width-1 downto 0));  -- result

end Dec;

-------------------------------------------------------------------------------

architecture Behavioral of Dec is

  signal Auns, Zuns : unsigned(width-1 downto 0);  -- unsigned

begin

  -- type conversion: std_logic_vector -> unsigned
  Auns <= unsigned(A);

  -- decrement
  Zuns <= Auns - 1;

  -- type conversion: unsigned -> std_logic_vector
  Z <= std_logic_vector(Zuns);

end Behavioral;

-------------------------------------------------------------------------------

architecture Structural of Dec is 

  signal AI : std_logic_vector(width-1 downto 0);  -- A inverted
  signal PO : std_logic_vector(width-1 downto 0);  -- prefix propagate out

begin

  -- invert A for decrement
  AI <= not A;
  
  -- calculate prefix output propagate signal
  prefix : PrefixAnd
    generic map (width, speed)
    port map (AI, PO);

  -- calculate result bits
  Z <= A xor PO(width-2 downto 0) & '1';

end Structural;

-------------------------------------------------------------------------------