redand.vhd

来自「Cadence的VHDL运算库包」· VHDL 代码 · 共 73 行

-------------------------------------------------------------------------------
-- Title       : Reduce AND
-- Project     : VHDL Library of Arithmetic Units
-------------------------------------------------------------------------------
-- File        : RedAnd.vhd
-- Author      : Reto Zimmermann  <[e-mail]>
-- Company     : Integrated Systems Laboratory, ETH Zurich
-- Date        : 1998/01/11
-------------------------------------------------------------------------------
-- Copyright (c) 1998 Integrated Systems Laboratory, ETH Zurich
-------------------------------------------------------------------------------
-- Description :
-- AND all bits of the input vector.
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
library arith_lib;
use arith_lib.arith_lib.all;

-------------------------------------------------------------------------------

entity RedAnd is

  generic (width : positive := 8);  	-- word width

  port (A : in std_logic_vector(width-1 downto 0);  -- input vector
	Z : out std_logic);		-- output bit

end RedAnd;

-------------------------------------------------------------------------------

architecture Behavioral of RedAnd is

begin

  -- AND all bits
  reduceAnd : process (A)
    variable zv : std_logic;
  begin
    zv := A(0);
    for i in 1 to width-1 loop
      zv := zv and A(i);
    end loop;
    Z <= zv;
  end process reduceAnd;

end Behavioral;

-------------------------------------------------------------------------------

architecture Structural of RedAnd is 


begin

  -- AND all bits
  -- again behavioral description used (well handled by all synthesizers) 
  reduceAnd : process (A)
    variable zv : std_logic;
  begin
    zv := A(0);
    for i in 1 to width-1 loop
      zv := zv and A(i);
    end loop;
    Z <= zv;
  end process reduceAnd;

end Structural;

-------------------------------------------------------------------------------