cnt.vhd

Cadence的VHDL运算库包

-------------------------------------------------------------------------------
-- Title       : (m,k)-counter
-- Project     : VHDL Library of Arithmetic Units
-------------------------------------------------------------------------------
-- File        : Cnt.vhd
-- Author      : Reto Zimmermann  <[e-mail]>
-- Company     : Integrated Systems Laboratory, ETH Zurich
-- Date        : 1997/11/17
-------------------------------------------------------------------------------
-- Copyright (c) 1998 Integrated Systems Laboratory, ETH Zurich
-------------------------------------------------------------------------------
-- Description :
-- (m,k)-counter adds m bits. Result is sum vector of k bits.
-- Composed of (m,k)-counter slices. Condition: depth > 1.
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
library synergy;  use synergy.signed_arith.all;
library arith_lib;
use arith_lib.arith_lib.all;
use arith_lib.arith_utils.all;

-------------------------------------------------------------------------------

entity Cnt is

  generic (depth : positive := 18;	-- number of input bits
	   speed : speedType := fast);  -- performance parameter

  port (A : in std_logic_vector(depth-1 downto 0);  -- input bits
	S : out std_logic_vector(log2floor(depth) downto 0));  -- sum output

end Cnt;

-------------------------------------------------------------------------------

architecture Behavioral of Cnt is
  
begin

  count : process (A)
    variable st : unsigned(log2floor(depth) downto 0);
  begin
    st := (others => '0');
    for i in 0 to depth-1 loop
      if A(i) = '1' then
	st := st + 1;
      end if;
    end loop;
    S <= std_logic_vector(st);
  end process count;
  
end Behavioral;

-------------------------------------------------------------------------------

architecture Structural of Cnt is 

  constant m : positive := depth;  	-- number of input bits
  constant n : positive := log2floor(depth)+1;  -- number of output bits
  signal CT : std_logic_vector(m*n downto 0);  -- intermediate carries

begin

  -- input bits are first intermediate carries
  CT(m-1 downto 0) <= A;

  -- linear arrangement of (m,k)-counter slices
  bits : for i in 0 to n-3 generate
    slice : CntSlice
      generic map (m/2**i, speed)
      port map (CT(i*m+m/2**i-1 downto i*m), S(i),
		CT((i+1)*m+m/2**(i+1)-1 downto (i+1)*m));
  end generate bits;

  -- add third carry if only two exist
  even : if m/2**(n-2) = 2 generate
    CT((n-2)*m+2) <= '0';
  end generate even;

  -- full-adder for adding the last three carries
  fa0 : FullAdder
    port map (CT((n-2)*m), CT((n-2)*m+1), CT((n-2)*m+2), S(n-2), S(n-1));

end Structural;

-------------------------------------------------------------------------------