bin2gray.vhd
来自「Cadence的VHDL运算库包」· VHDL 代码 · 共 71 行
VHD
71 行
--------------------------------------------------------------------------------- Title : Binary-to-Gray converter-- Project : VHDL Library of Arithmetic Units--------------------------------------------------------------------------------- File : Bin2Gray.vhd-- Author : Reto Zimmermann <zimmi@iis.ee.ethz.ch>-- Company : Integrated Systems Laboratory, ETH Zurich-- Date : 1997/12/28--------------------------------------------------------------------------------- Copyright (c) 1998 Integrated Systems Laboratory, ETH Zurich--------------------------------------------------------------------------------- Description :-- Converts a number from binary to Gray representation.-------------------------------------------------------------------------------library ieee;use ieee.std_logic_1164.all;library arith_lib;use arith_lib.arith_lib.all;-------------------------------------------------------------------------------entity Bin2Gray is generic (width : positive := 8); -- word width port (B : in std_logic_vector(width-1 downto 0); -- binary input G : out std_logic_vector(width-1 downto 0)); -- Gray outputend Bin2Gray;-------------------------------------------------------------------------------architecture Behavioral of Bin2Gray is signal BT : std_logic_vector(width downto 0); -- temp.begin -- non-recursive description of binary to Gray conversion b2g : process (B) variable bv : std_logic_vector(width downto 0); begin bv := '0' & B; for i in 0 to width-1 loop G(i) <= bv(i+1) xor bv(i); end loop; end process b2g;end Behavioral;-------------------------------------------------------------------------------architecture Structural of Bin2Gray is signal BT : std_logic_vector(width downto 0); -- temp.begin -- expand B BT <= '0' & B; -- convert binary to Gray b2g : for i in 0 to width-1 generate G(i) <= BT(i+1) xor BT(i); end generate b2g;end Structural;-------------------------------------------------------------------------------
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