mulsgn.vhd

Cadence的VHDL运算库包

-------------------------------------------------------------------------------
-- Title       : Signed multiplier
-- Project     : VHDL Library of Arithmetic Units
-------------------------------------------------------------------------------
-- File        : MulSgn.vhd
-- Author      : Reto Zimmermann  <[e-mail]>
-- Company     : Integrated Systems Laboratory, ETH Zurich
-- Date        : 1997/11/11
-------------------------------------------------------------------------------
-- Copyright (c) 1998 Integrated Systems Laboratory, ETH Zurich
-------------------------------------------------------------------------------
-- Description :
-- Multiplier for signed numbers (Baugh-Wooley) using carry-save adder and
-- final adder.
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
library synergy;  use synergy.signed_arith.all;
library arith_lib;
use arith_lib.arith_lib.all;

-------------------------------------------------------------------------------

entity MulSgn is

  generic (widthX : positive := 8;	-- word width of X (X <= Y)
	   widthY : positive := 8;	-- word width of Y
	   speed : speedType := fast);	-- performance parameter

  port (X : in std_logic_vector(widthX-1 downto 0);  -- multiplier
	Y : in std_logic_vector(widthY-1 downto 0);  -- multiplicand
        P : out std_logic_vector(widthX+widthY-1 downto 0));  -- product

end MulSgn;

-------------------------------------------------------------------------------

architecture Behavioral of MulSgn is

  signal Xuns : signed(widthX-1 downto 0);  -- signed
  signal Yuns : signed(widthY-1 downto 0);  -- signed
  signal Puns : signed(widthX+widthY-1 downto 0);  -- signed

begin

  -- type conversion: std_logic_vector -> signed
  Xuns <= signed(X);
  Yuns <= signed(Y);

  -- multiplication
  Puns <= Xuns * Yuns;

  -- type conversion: signed -> std_logic_vector
  P <= std_logic_vector(Puns);

end Behavioral;

-------------------------------------------------------------------------------

architecture Structural of MulSgn is 

						-- partial products
  signal PP : std_logic_vector((widthX+2)*(widthX+widthY)-1 downto 0);
						-- intermediate sum/carry bits
  signal ST, CT : std_logic_vector(widthX+widthY-1 downto 0); 

begin

  -- generation of partial products
  ppGen : MulPPGenSgn
    generic map (widthX, widthY)
    port map (X, Y, PP);

  -- carry-save addition of partial products
  csvAdd : AddMopCsv
    generic map (widthX+widthY, widthX+2, speed)
    port map (PP, ST, CT);

  -- final carry-propagate addition
  cpAdd : Add
    generic map (widthX+widthY, speed)
    port map (ST, CT, P);

end Structural;

-------------------------------------------------------------------------------