encode.vhd

Cadence的VHDL运算库包

-------------------------------------------------------------------------------
-- Title       : Encoder
-- Project     : VHDL Library of Arithmetic Units
-------------------------------------------------------------------------------
-- File        : Encode.vhd
-- Author      : Reto Zimmermann  <[e-mail]>
-- Company     : Integrated Systems Laboratory, ETH Zurich
-- Date        : 1998/01/09
-------------------------------------------------------------------------------
-- Copyright (c) 1998 Integrated Systems Laboratory, ETH Zurich
-------------------------------------------------------------------------------
-- Description :
-- Encodes the position of a '1' in the input vector into a binary number.
-- Example: A = "00100000" -> Z = "101".
-- Condition: exactly one bit of input vector A is '1'.
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
library synergy;  use synergy.signed_arith.all;
library arith_lib;
use arith_lib.arith_lib.all;
use arith_lib.arith_utils.all;

-------------------------------------------------------------------------------

entity Encode is

  generic (width : positive := 8);  	-- word width

  port (A : in std_logic_vector(width-1 downto 0);  -- input vector
	Z : out std_logic_vector(log2ceil(width)-1 downto 0)); -- enc. output

end Encode;

-------------------------------------------------------------------------------

architecture Behavioral of Encode is

begin

  -- encoding
  enc : process (A)
    variable zv : unsigned(log2ceil(width)-1 downto 0);
  begin
    zv := (others => '0');
    for i in 0 to width-1 loop
      if A(i) = '1' then
	zv := conv_unsigned(i, log2ceil(width));
      end if;
    end loop;
    Z <= std_logic_vector(zv);
  end process enc;

end Behavioral;

-------------------------------------------------------------------------------

architecture Structural of Encode is

  constant n : positive := width;
  constant m : positive := log2ceil(width);

begin

  -- example: n = 8, m = 3
  --   Z(0) = A(7) or A(5) or A(3) or A(1)
  --   Z(1) = A(7) or A(6) or A(3) or A(2)
  --   Z(2) = A(7) or A(6) or A(5) or A(4)
  -- indices correspond to position of black nodes in Sklansky parallel-prefix
  -- algorithm
  outbit : for l in 1 to m generate
    inbit : process (A)
      variable zv : std_logic;
    begin
      zv := '0';
      for k in 0 to 2**(m-l) - 1 loop
	for i in 0 to 2**(l-1) - 1 loop
	  if (k*2**l + 2**(l-1) + i) < n then
	    zv := zv or A(k*2**l + 2**(l-1) + i);
	  else
	    zv := zv;
	  end if;
	end loop;
      end loop;
      Z(l-1) <= zv;
    end process inbit;
  end generate outbit;

end Structural;

-------------------------------------------------------------------------------