reg.vhd

Cadence的VHDL运算库包

-------------------------------------------------------------------------------
-- Title       : Register
-- Project     : VHDL Library of Arithmetic Units
-------------------------------------------------------------------------------
-- File        : Reg.vhd
-- Author      : Reto Zimmermann  <[e-mail]>
-- Company     : Integrated Systems Laboratory, ETH Zurich
-- Date        : 1997/11/04
-------------------------------------------------------------------------------
-- Copyright (c) 1998 Integrated Systems Laboratory, ETH Zurich
-------------------------------------------------------------------------------
-- Description :
-- Register for pipelining.
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
library arith_lib;
use arith_lib.arith_lib.all;

-------------------------------------------------------------------------------

entity Reg is

  generic (width : positive := 8);  	-- word width

  port (CLK : in std_logic;  		-- clock
	RST : in std_logic;  		-- reset
        D : in std_logic_vector(width-1 downto 0);  -- data input
	Q : out std_logic_vector(width-1 downto 0));  -- data output

end Reg;

-------------------------------------------------------------------------------

architecture Structural of Reg is 

begin

  -- purpose: memorizing process to register inputs
  reg : process (CLK, RST)
  begin
    if RST = '0' then
      Q <= (others => '0');
    elsif CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process reg;

end Structural;

-------------------------------------------------------------------------------