incgrayc.vhd

Cadence的VHDL运算库包

-------------------------------------------------------------------------------
-- Title       : Parallel-prefix Gray Incrementer with carry-in
-- Project     : VHDL Library of Arithmetic Units
-------------------------------------------------------------------------------
-- File        : IncGrayC.vhd
-- Author      : Reto Zimmermann  <[e-mail]>
-- Company     : Integrated Systems Laboratory, ETH Zurich
-- Date        : 1998/01/12
-------------------------------------------------------------------------------
-- Copyright (c) 1998 Integrated Systems Laboratory, ETH Zurich
-------------------------------------------------------------------------------
-- Description :
-- Incrementer for Gray numbers using parallel-prefix propagate-lookahead
-- logic with:
--   - carry-in (CI)
-- Bases on the following algorithm:
--   P = A(n-1) xor A(n-2) xor ... xor A(0)
--   Z(0) = A(0) xnor P
--   Z(i) = A(i) xor (A(i-1) and not A(i-2) and not A(i-3) ...
--                           and not A(0) and P)              ; i = 1, ..., n-2
--   Z(n-1) = A(n-1) xor (not A(n-3) and not A(n-4) ... and not A(0) and P)
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
library synergy;  use synergy.signed_arith.all;
library arith_lib;
use arith_lib.arith_lib.all;

-------------------------------------------------------------------------------

entity IncGrayC is

  generic (width : positive := 16;  	-- word width
	   speed : speedType := slow);  -- performance parameter

  port (A : in std_logic_vector(width-1 downto 0);  -- operand
        CI : in std_logic;  		-- carry in
	Z : out std_logic_vector(width-1 downto 0));  -- result

end IncGrayC;

-------------------------------------------------------------------------------

architecture Behavioral of IncGrayC is

  signal BI, BO : std_logic_vector(width-1 downto 0);  -- unsigned
  signal BIuns, BOuns, CIuns : unsigned(width-1 downto 0);  -- unsigned

begin

  -- Gray to binary conversion
  g2b : process (A)
    variable biv : std_logic_vector(width downto 0);
  begin
    biv(width) := '0';
    for i in width-1 downto 0 loop
      biv(i) := biv(i+1) xor A(i);
    end loop;
    
    BI <= biv(width-1 downto 0);
  end process g2b;

  -- type conversion: std_logic_vector -> unsigned
  BIuns <= unsigned(BI);
  CIuns <= (0 => CI, others => '0');

  -- Increment
  BOuns <= BIuns + Ciuns;

  -- type conversion: unsigned -> std_logic_vector
  BO <= std_logic_vector(BOuns);

  -- binary to Gray conversion
  b2g : process (BO)
    variable bov : std_logic_vector(width downto 0);
  begin
    bov := '0' & BO;
    for i in 0 to width-1 loop
      Z(i) <= bov(i+1) xor bov(i);
    end loop;
  end process b2g;

end Behavioral;

-------------------------------------------------------------------------------

architecture Structural of IncGrayC is 

  signal PI, PO : std_logic_vector(width-2 downto 0);  -- prefix prop. in/out
  signal P, PT : std_logic;  		-- parity bit
  signal T1 : std_logic_vector(width-1 downto 2);  -- temp.
  signal T2 : std_logic_vector(width-1 downto 0);  -- temp.

begin

  -- calculate parity bit P
  parity : RedXor
    generic map (width)
    port map (A, P);

  -- calculate prefix input propagate signal (PI = not A(i))
  PI(width-2 downto 1) <= not A(width-3 downto 0);
  -- feed slow P signal into prefix circuit for slow architecture
  -- consider CI here for bits 2, ..., n-1
  speed1 : if speed = slow generate
    PI(0) <= P and CI;
  end generate speed1;
  speed2 : if speed /= slow generate
    PI(0) <= CI;
  end generate speed2;

  -- calculate prefix output prop. signal (PO = not A(i-2) ... and not A(0))
  prefix : PrefixAnd
    generic map (width-1, speed)
    port map (PI, PO);

  -- calculate (A and PO)
  T1(width-2 downto 2) <= A(width-3 downto 1) and PO(width-3 downto 1);
  -- special case
  T1(width-1) <= PO(width-2);

  -- calculate (T1 and P) in fast architecture
  bits : for i in width-1 downto 2 generate
    speed3 : if speed = slow generate
      T2(i) <= T1(i);
    end generate speed3;
    speed4 : if speed /= slow generate
      T2(i) <= T1(i) and P;
    end generate speed4;
  end generate bits;
  -- special cases, consider CI hier for bits 0 and 1
  T2(1) <= A(0) and P and CI;
  T2(0) <= not (P or not CI);

  -- calculate result bits
  Z <= A xor T2(width-1 downto 0);

end Structural;

-------------------------------------------------------------------------------