cnt60.tan.rpt

是我们在在实验室做的摸60计数

; N/A   ; None         ; 15.524 ns  ; q_tmp[6] ; led7s0[6] ; clk        ;
; N/A   ; None         ; 15.521 ns  ; q_tmp[6] ; led7s0[5] ; clk        ;
; N/A   ; None         ; 15.435 ns  ; q_tmp[7] ; led7s0[2] ; clk        ;
; N/A   ; None         ; 15.372 ns  ; q_tmp[5] ; led7s0[4] ; clk        ;
; N/A   ; None         ; 15.367 ns  ; q_tmp[5] ; led7s0[6] ; clk        ;
; N/A   ; None         ; 15.364 ns  ; q_tmp[5] ; led7s0[5] ; clk        ;
; N/A   ; None         ; 15.261 ns  ; q_tmp[7] ; led7s0[3] ; clk        ;
; N/A   ; None         ; 15.072 ns  ; q_tmp[6] ; led7s1[2] ; clk        ;
; N/A   ; None         ; 15.059 ns  ; q_tmp[6] ; led7s1[0] ; clk        ;
; N/A   ; None         ; 15.051 ns  ; q_tmp[6] ; led7s1[4] ; clk        ;
; N/A   ; None         ; 15.051 ns  ; q_tmp[6] ; led7s1[1] ; clk        ;
; N/A   ; None         ; 15.049 ns  ; q_tmp[6] ; led7s1[6] ; clk        ;
; N/A   ; None         ; 15.049 ns  ; q_tmp[6] ; led7s1[5] ; clk        ;
; N/A   ; None         ; 15.043 ns  ; q_tmp[6] ; led7s1[3] ; clk        ;
; N/A   ; None         ; 14.955 ns  ; q_tmp[7] ; led7s0[4] ; clk        ;
; N/A   ; None         ; 14.950 ns  ; q_tmp[7] ; led7s0[6] ; clk        ;
; N/A   ; None         ; 14.947 ns  ; q_tmp[7] ; led7s0[5] ; clk        ;
; N/A   ; None         ; 10.235 ns  ; q_tmp[0] ; led7s0[0] ; clk        ;
; N/A   ; None         ; 10.082 ns  ; q_tmp[0] ; led7s0[1] ; clk        ;
; N/A   ; None         ; 9.321 ns   ; q_tmp[0] ; led7s0[2] ; clk        ;
; N/A   ; None         ; 9.126 ns   ; q_tmp[0] ; led7s0[3] ; clk        ;
; N/A   ; None         ; 8.833 ns   ; q_tmp[0] ; led7s0[4] ; clk        ;
; N/A   ; None         ; 8.831 ns   ; q_tmp[0] ; led7s0[6] ; clk        ;
; N/A   ; None         ; 8.815 ns   ; q_tmp[0] ; led7s0[5] ; clk        ;
+-------+--------------+------------+----------+-----------+------------+


+----------------------------------------------------------------------+
; th                                                                   ;
+---------------+-------------+-----------+------+----------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To       ; To Clock ;
+---------------+-------------+-----------+------+----------+----------+
; N/A           ; None        ; -6.749 ns ; en   ; q_tmp[4] ; clk      ;
; N/A           ; None        ; -6.749 ns ; en   ; q_tmp[6] ; clk      ;
; N/A           ; None        ; -6.749 ns ; en   ; q_tmp[3] ; clk      ;
; N/A           ; None        ; -6.749 ns ; en   ; q_tmp[2] ; clk      ;
; N/A           ; None        ; -6.749 ns ; en   ; q_tmp[7] ; clk      ;
; N/A           ; None        ; -6.816 ns ; en   ; q_tmp[5] ; clk      ;
; N/A           ; None        ; -6.816 ns ; en   ; q_tmp[0] ; clk      ;
; N/A           ; None        ; -7.085 ns ; en   ; q_tmp[1] ; clk      ;
+---------------+-------------+-----------+------+----------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Tue Oct 17 10:23:14 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off cnt60 -c cnt60 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 266.1 MHz between source register "q_tmp[1]" and destination register "q_tmp[2]" (period= 3.758 ns)
    Info: + Longest register to register delay is 3.497 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X25_Y7_N5; Fanout = 17; REG Node = 'q_tmp[1]'
        Info: 2: + IC(0.765 ns) + CELL(0.432 ns) = 1.197 ns; Loc. = LC_X24_Y7_N1; Fanout = 2; COMB Node = 'add~851COUT1_904'
        Info: 3: + IC(0.000 ns) + CELL(0.608 ns) = 1.805 ns; Loc. = LC_X24_Y7_N2; Fanout = 1; COMB Node = 'add~879'
        Info: 4: + IC(1.085 ns) + CELL(0.607 ns) = 3.497 ns; Loc. = LC_X23_Y7_N5; Fanout = 23; REG Node = 'q_tmp[2]'
        Info: Total cell delay = 1.647 ns ( 47.10 % )
        Info: Total interconnect delay = 1.850 ns ( 52.90 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 2.781 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 8; CLK Node = 'clk'
            Info: 2: + IC(0.601 ns) + CELL(0.711 ns) = 2.781 ns; Loc. = LC_X23_Y7_N5; Fanout = 23; REG Node = 'q_tmp[2]'
            Info: Total cell delay = 2.180 ns ( 78.39 % )
            Info: Total interconnect delay = 0.601 ns ( 21.61 % )
        Info: - Longest clock path from clock "clk" to source register is 2.781 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 8; CLK Node = 'clk'
            Info: 2: + IC(0.601 ns) + CELL(0.711 ns) = 2.781 ns; Loc. = LC_X25_Y7_N5; Fanout = 17; REG Node = 'q_tmp[1]'
            Info: Total cell delay = 2.180 ns ( 78.39 % )
            Info: Total interconnect delay = 0.601 ns ( 21.61 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Micro setup delay of destination is 0.037 ns
Info: tsu for register "q_tmp[1]" (data pin = "en", clock pin = "clk") is 7.137 ns
    Info: + Longest pin to register delay is 9.881 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_11; Fanout = 8; PIN Node = 'en'
        Info: 2: + IC(7.545 ns) + CELL(0.867 ns) = 9.881 ns; Loc. = LC_X25_Y7_N5; Fanout = 17; REG Node = 'q_tmp[1]'
        Info: Total cell delay = 2.336 ns ( 23.64 % )
        Info: Total interconnect delay = 7.545 ns ( 76.36 % )
    Info: + Micro setup delay of destination is 0.037 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.781 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 8; CLK Node = 'clk'
        Info: 2: + IC(0.601 ns) + CELL(0.711 ns) = 2.781 ns; Loc. = LC_X25_Y7_N5; Fanout = 17; REG Node = 'q_tmp[1]'
        Info: Total cell delay = 2.180 ns ( 78.39 % )
        Info: Total interconnect delay = 0.601 ns ( 21.61 % )
Info: tco from clock "clk" to destination pin "led7s0[0]" through register "q_tmp[2]" is 17.844 ns
    Info: + Longest clock path from clock "clk" to source register is 2.781 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 8; CLK Node = 'clk'
        Info: 2: + IC(0.601 ns) + CELL(0.711 ns) = 2.781 ns; Loc. = LC_X23_Y7_N5; Fanout = 23; REG Node = 'q_tmp[2]'
        Info: Total cell delay = 2.180 ns ( 78.39 % )
        Info: Total interconnect delay = 0.601 ns ( 21.61 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 14.839 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X23_Y7_N5; Fanout = 23; REG Node = 'q_tmp[2]'
        Info: 2: + IC(1.266 ns) + CELL(0.114 ns) = 1.380 ns; Loc. = LC_X25_Y7_N5; Fanout = 2; COMB Node = 'LessThan~622'
        Info: 3: + IC(0.401 ns) + CELL(0.442 ns) = 2.223 ns; Loc. = LC_X25_Y7_N1; Fanout = 3; COMB Node = 'LessThan~623'
        Info: 4: + IC(0.674 ns) + CELL(0.442 ns) = 3.339 ns; Loc. = LC_X25_Y7_N3; Fanout = 2; COMB Node = 'q_bcd~3212'
        Info: 5: + IC(1.237 ns) + CELL(0.442 ns) = 5.018 ns; Loc. = LC_X24_Y6_N8; Fanout = 1; COMB Node = 'q_bcd[2]~3221'
        Info: 6: + IC(1.555 ns) + CELL(0.292 ns) = 6.865 ns; Loc. = LC_X22_Y7_N9; Fanout = 1; COMB Node = 'q_bcd[2]~3222'
        Info: 7: + IC(1.541 ns) + CELL(0.292 ns) = 8.698 ns; Loc. = LC_X24_Y5_N3; Fanout = 7; COMB Node = 'q_bcd[2]~3223'
        Info: 8: + IC(0.518 ns) + CELL(0.442 ns) = 9.658 ns; Loc. = LC_X24_Y5_N2; Fanout = 1; COMB Node = 'Mux~396'
        Info: 9: + IC(3.073 ns) + CELL(2.108 ns) = 14.839 ns; Loc. = PIN_51; Fanout = 0; PIN Node = 'led7s0[0]'
        Info: Total cell delay = 4.574 ns ( 30.82 % )
        Info: Total interconnect delay = 10.265 ns ( 69.18 % )
Info: th for register "q_tmp[4]" (data pin = "en", clock pin = "clk") is -6.749 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.781 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 8; CLK Node = 'clk'
        Info: 2: + IC(0.601 ns) + CELL(0.711 ns) = 2.781 ns; Loc. = LC_X23_Y7_N3; Fanout = 25; REG Node = 'q_tmp[4]'
        Info: Total cell delay = 2.180 ns ( 78.39 % )
        Info: Total interconnect delay = 0.601 ns ( 21.61 % )
    Info: + Micro hold delay of destination is 0.015 ns
    Info: - Shortest pin to register delay is 9.545 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_11; Fanout = 8; PIN Node = 'en'
        Info: 2: + IC(7.209 ns) + CELL(0.867 ns) = 9.545 ns; Loc. = LC_X23_Y7_N3; Fanout = 25; REG Node = 'q_tmp[4]'
        Info: Total cell delay = 2.336 ns ( 24.47 % )
        Info: Total interconnect delay = 7.209 ns ( 75.53 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Tue Oct 17 10:23:14 2006
    Info: Elapsed time: 00:00:01