cnt60.tan.qmsg

是我们在在实验室做的摸60计数

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register q_tmp\[1\] register q_tmp\[2\] 266.1 MHz 3.758 ns Internal " "Info: Clock \"clk\" has Internal fmax of 266.1 MHz between source register \"q_tmp\[1\]\" and destination register \"q_tmp\[2\]\" (period= 3.758 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.497 ns + Longest register register " "Info: + Longest register to register delay is 3.497 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns q_tmp\[1\] 1 REG LC_X25_Y7_N5 17 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X25_Y7_N5; Fanout = 17; REG Node = 'q_tmp\[1\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt60" "UNKNOWN" "V1" "E:/20035024/count60/db/cnt60.quartus_db" { Floorplan "E:/20035024/count60/" "" "" { q_tmp[1] } "NODE_NAME" } "" } } { "cnt60.vhd" "" { Text "E:/20035024/count60/cnt60.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.765 ns) + CELL(0.432 ns) 1.197 ns add~851COUT1_904 2 COMB LC_X24_Y7_N1 2 " "Info: 2: + IC(0.765 ns) + CELL(0.432 ns) = 1.197 ns; Loc. = LC_X24_Y7_N1; Fanout = 2; COMB Node = 'add~851COUT1_904'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt60" "UNKNOWN" "V1" "E:/20035024/count60/db/cnt60.quartus_db" { Floorplan "E:/20035024/count60/" "" "1.197 ns" { q_tmp[1] add~851COUT1_904 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.608 ns) 1.805 ns add~879 3 COMB LC_X24_Y7_N2 1 " "Info: 3: + IC(0.000 ns) + CELL(0.608 ns) = 1.805 ns; Loc. = LC_X24_Y7_N2; Fanout = 1; COMB Node = 'add~879'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt60" "UNKNOWN" "V1" "E:/20035024/count60/db/cnt60.quartus_db" { Floorplan "E:/20035024/count60/" "" "0.608 ns" { add~851COUT1_904 add~879 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.085 ns) + CELL(0.607 ns) 3.497 ns q_tmp\[2\] 4 REG LC_X23_Y7_N5 23 " "Info: 4: + IC(1.085 ns) + CELL(0.607 ns) = 3.497 ns; Loc. = LC_X23_Y7_N5; Fanout = 23; REG Node = 'q_tmp\[2\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt60" "UNKNOWN" "V1" "E:/20035024/count60/db/cnt60.quartus_db" { Floorplan "E:/20035024/count60/" "" "1.692 ns" { add~879 q_tmp[2] } "NODE_NAME" } "" } } { "cnt60.vhd" "" { Text "E:/20035024/count60/cnt60.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.647 ns ( 47.10 % ) " "Info: Total cell delay = 1.647 ns ( 47.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.850 ns ( 52.90 % ) " "Info: Total interconnect delay = 1.850 ns ( 52.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt60" "UNKNOWN" "V1" "E:/20035024/count60/db/cnt60.quartus_db" { Floorplan "E:/20035024/count60/" "" "3.497 ns" { q_tmp[1] add~851COUT1_904 add~879 q_tmp[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.497 ns" { q_tmp[1] add~851COUT1_904 add~879 q_tmp[2] } { 0.000ns 0.765ns 0.000ns 1.085ns } { 0.000ns 0.432ns 0.608ns 0.607ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.781 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.781 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_93 8 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 8; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt60" "UNKNOWN" "V1" "E:/20035024/count60/db/cnt60.quartus_db" { Floorplan "E:/20035024/count60/" "" "" { clk } "NODE_NAME" } "" } } { "cnt60.vhd" "" { Text "E:/20035024/count60/cnt60.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.601 ns) + CELL(0.711 ns) 2.781 ns q_tmp\[2\] 2 REG LC_X23_Y7_N5 23 " "Info: 2: + IC(0.601 ns) + CELL(0.711 ns) = 2.781 ns; Loc. = LC_X23_Y7_N5; Fanout = 23; REG Node = 'q_tmp\[2\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt60" "UNKNOWN" "V1" "E:/20035024/count60/db/cnt60.quartus_db" { Floorplan "E:/20035024/count60/" "" "1.312 ns" { clk q_tmp[2] } "NODE_NAME" } "" } } { "cnt60.vhd" "" { Text "E:/20035024/count60/cnt60.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.39 % ) " "Info: Total cell delay = 2.180 ns ( 78.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.601 ns ( 21.61 % ) " "Info: Total interconnect delay = 0.601 ns ( 21.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt60" "UNKNOWN" "V1" "E:/20035024/count60/db/cnt60.quartus_db" { Floorplan "E:/20035024/count60/" "" "2.781 ns" { clk q_tmp[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.781 ns" { clk clk~out0 q_tmp[2] } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.781 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.781 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_93 8 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 8; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt60" "UNKNOWN" "V1" "E:/20035024/count60/db/cnt60.quartus_db" { Floorplan "E:/20035024/count60/" "" "" { clk } "NODE_NAME" } "" } } { "cnt60.vhd" "" { Text "E:/20035024/count60/cnt60.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.601 ns) + CELL(0.711 ns) 2.781 ns q_tmp\[1\] 2 REG LC_X25_Y7_N5 17 " "Info: 2: + IC(0.601 ns) + CELL(0.711 ns) = 2.781 ns; Loc. = LC_X25_Y7_N5; Fanout = 17; REG Node = 'q_tmp\[1\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt60" "UNKNOWN" "V1" "E:/20035024/count60/db/cnt60.quartus_db" { Floorplan "E:/20035024/count60/" "" "1.312 ns" { clk q_tmp[1] } "NODE_NAME" } "" } } { "cnt60.vhd" "" { Text "E:/20035024/count60/cnt60.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.39 % ) " "Info: Total cell delay = 2.180 ns ( 78.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.601 ns ( 21.61 % ) " "Info: Total interconnect delay = 0.601 ns ( 21.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt60" "UNKNOWN" "V1" "E:/20035024/count60/db/cnt60.quartus_db" { Floorplan "E:/20035024/count60/" "" "2.781 ns" { clk q_tmp[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.781 ns" { clk clk~out0 q_tmp[1] } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt60" "UNKNOWN" "V1" "E:/20035024/count60/db/cnt60.quartus_db" { Floorplan "E:/20035024/count60/" "" "2.781 ns" { clk q_tmp[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.781 ns" { clk clk~out0 q_tmp[2] } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt60" "UNKNOWN" "V1" "E:/20035024/count60/db/cnt60.quartus_db" { Floorplan "E:/20035024/count60/" "" "2.781 ns" { clk q_tmp[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.781 ns" { clk clk~out0 q_tmp[1] } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "cnt60.vhd" "" { Text "E:/20035024/count60/cnt60.vhd" 21 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "cnt60.vhd" "" { Text "E:/20035024/count60/cnt60.vhd" 21 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt60" "UNKNOWN" "V1" "E:/20035024/count60/db/cnt60.quartus_db" { Floorplan "E:/20035024/count60/" "" "3.497 ns" { q_tmp[1] add~851COUT1_904 add~879 q_tmp[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.497 ns" { q_tmp[1] add~851COUT1_904 add~879 q_tmp[2] } { 0.000ns 0.765ns 0.000ns 1.085ns } { 0.000ns 0.432ns 0.608ns 0.607ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt60" "UNKNOWN" "V1" "E:/20035024/count60/db/cnt60.quartus_db" { Floorplan "E:/20035024/count60/" "" "2.781 ns" { clk q_tmp[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.781 ns" { clk clk~out0 q_tmp[2] } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt60" "UNKNOWN" "V1" "E:/20035024/count60/db/cnt60.quartus_db" { Floorplan "E:/20035024/count60/" "" "2.781 ns" { clk q_tmp[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.781 ns" { clk clk~out0 q_tmp[1] } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "q_tmp\[1\] en clk 7.137 ns register " "Info: tsu for register \"q_tmp\[1\]\" (data pin = \"en\", clock pin = \"clk\") is 7.137 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.881 ns + Longest pin register " "Info: + Longest pin to register delay is 9.881 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns en 1 PIN PIN_11 8 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_11; Fanout = 8; PIN Node = 'en'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt60" "UNKNOWN" "V1" "E:/20035024/count60/db/cnt60.quartus_db" { Floorplan "E:/20035024/count60/" "" "" { en } "NODE_NAME" } "" } } { "cnt60.vhd" "" { Text "E:/20035024/count60/cnt60.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(7.545 ns) + CELL(0.867 ns) 9.881 ns q_tmp\[1\] 2 REG LC_X25_Y7_N5 17 " "Info: 2: + IC(7.545 ns) + CELL(0.867 ns) = 9.881 ns; Loc. = LC_X25_Y7_N5; Fanout = 17; REG Node = 'q_tmp\[1\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt60" "UNKNOWN" "V1" "E:/20035024/count60/db/cnt60.quartus_db" { Floorplan "E:/20035024/count60/" "" "8.412 ns" { en q_tmp[1] } "NODE_NAME" } "" } } { "cnt60.vhd" "" { Text "E:/20035024/count60/cnt60.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.336 ns ( 23.64 % ) " "Info: Total cell delay = 2.336 ns ( 23.64 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.545 ns ( 76.36 % ) " "Info: Total interconnect delay = 7.545 ns ( 76.36 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt60" "UNKNOWN" "V1" "E:/20035024/count60/db/cnt60.quartus_db" { Floorplan "E:/20035024/count60/" "" "9.881 ns" { en q_tmp[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "9.881 ns" { en en~out0 q_tmp[1] } { 0.000ns 0.000ns 7.545ns } { 0.000ns 1.469ns 0.867ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "cnt60.vhd" "" { Text "E:/20035024/count60/cnt60.vhd" 21 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.781 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.781 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_93 8 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 8; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt60" "UNKNOWN" "V1" "E:/20035024/count60/db/cnt60.quartus_db" { Floorplan "E:/20035024/count60/" "" "" { clk } "NODE_NAME" } "" } } { "cnt60.vhd" "" { Text "E:/20035024/count60/cnt60.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.601 ns) + CELL(0.711 ns) 2.781 ns q_tmp\[1\] 2 REG LC_X25_Y7_N5 17 " "Info: 2: + IC(0.601 ns) + CELL(0.711 ns) = 2.781 ns; Loc. = LC_X25_Y7_N5; Fanout = 17; REG Node = 'q_tmp\[1\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt60" "UNKNOWN" "V1" "E:/20035024/count60/db/cnt60.quartus_db" { Floorplan "E:/20035024/count60/" "" "1.312 ns" { clk q_tmp[1] } "NODE_NAME" } "" } } { "cnt60.vhd" "" { Text "E:/20035024/count60/cnt60.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.39 % ) " "Info: Total cell delay = 2.180 ns ( 78.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.601 ns ( 21.61 % ) " "Info: Total interconnect delay = 0.601 ns ( 21.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt60" "UNKNOWN" "V1" "E:/20035024/count60/db/cnt60.quartus_db" { Floorplan "E:/20035024/count60/" "" "2.781 ns" { clk q_tmp[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.781 ns" { clk clk~out0 q_tmp[1] } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt60" "UNKNOWN" "V1" "E:/20035024/count60/db/cnt60.quartus_db" { Floorplan "E:/20035024/count60/" "" "9.881 ns" { en q_tmp[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "9.881 ns" { en en~out0 q_tmp[1] } { 0.000ns 0.000ns 7.545ns } { 0.000ns 1.469ns 0.867ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt60" "UNKNOWN" "V1" "E:/20035024/count60/db/cnt60.quartus_db" { Floorplan "E:/20035024/count60/" "" "2.781 ns" { clk q_tmp[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.781 ns" { clk clk~out0 q_tmp[1] } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk led7s0\[0\] q_tmp\[2\] 17.844 ns register " "Info: tco from clock \"clk\" to destination pin \"led7s0\[0\]\" through register \"q_tmp\[2\]\" is 17.844 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.781 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.781 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_93 8 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 8; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt60" "UNKNOWN" "V1" "E:/20035024/count60/db/cnt60.quartus_db" { Floorplan "E:/20035024/count60/" "" "" { clk } "NODE_NAME" } "" } } { "cnt60.vhd" "" { Text "E:/20035024/count60/cnt60.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.601 ns) + CELL(0.711 ns) 2.781 ns q_tmp\[2\] 2 REG LC_X23_Y7_N5 23 " "Info: 2: + IC(0.601 ns) + CELL(0.711 ns) = 2.781 ns; Loc. = LC_X23_Y7_N5; Fanout = 23; REG Node = 'q_tmp\[2\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt60" "UNKNOWN" "V1" "E:/20035024/count60/db/cnt60.quartus_db" { Floorplan "E:/20035024/count60/" "" "1.312 ns" { clk q_tmp[2] } "NODE_NAME" } "" } } { "cnt60.vhd" "" { Text "E:/20035024/count60/cnt60.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.39 % ) " "Info: Total cell delay = 2.180 ns ( 78.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.601 ns ( 21.61 % ) " "Info: Total interconnect delay = 0.601 ns ( 21.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt60" "UNKNOWN" "V1" "E:/20035024/count60/db/cnt60.quartus_db" { Floorplan "E:/20035024/count60/" "" "2.781 ns" { clk q_tmp[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.781 ns" { clk clk~out0 q_tmp[2] } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "cnt60.vhd" "" { Text "E:/20035024/count60/cnt60.vhd" 21 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "14.839 ns + Longest register pin " "Info: + Longest register to pin delay is 14.839 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns q_tmp\[2\] 1 REG LC_X23_Y7_N5 23 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X23_Y7_N5; Fanout = 23; REG Node = 'q_tmp\[2\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt60" "UNKNOWN" "V1" "E:/20035024/count60/db/cnt60.quartus_db" { Floorplan "E:/20035024/count60/" "" "" { q_tmp[2] } "NODE_NAME" } "" } } { "cnt60.vhd" "" { Text "E:/20035024/count60/cnt60.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.266 ns) + CELL(0.114 ns) 1.380 ns LessThan~622 2 COMB LC_X25_Y7_N5 2 " "Info: 2: + IC(1.266 ns) + CELL(0.114 ns) = 1.380 ns; Loc. = LC_X25_Y7_N5; Fanout = 2; COMB Node = 'LessThan~622'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt60" "UNKNOWN" "V1" "E:/20035024/count60/db/cnt60.quartus_db" { Floorplan "E:/20035024/count60/" "" "1.380 ns" { q_tmp[2] LessThan~622 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.401 ns) + CELL(0.442 ns) 2.223 ns LessThan~623 3 COMB LC_X25_Y7_N1 3 " "Info: 3: + IC(0.401 ns) + CELL(0.442 ns) = 2.223 ns; Loc. = LC_X25_Y7_N1; Fanout = 3; COMB Node = 'LessThan~623'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt60" "UNKNOWN" "V1" "E:/20035024/count60/db/cnt60.quartus_db" { Floorplan "E:/20035024/count60/" "" "0.843 ns" { LessThan~622 LessThan~623 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.674 ns) + CELL(0.442 ns) 3.339 ns q_bcd~3212 4 COMB LC_X25_Y7_N3 2 " "Info: 4: + IC(0.674 ns) + CELL(0.442 ns) = 3.339 ns; Loc. = LC_X25_Y7_N3; Fanout = 2; COMB Node = 'q_bcd~3212'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt60" "UNKNOWN" "V1" "E:/20035024/count60/db/cnt60.quartus_db" { Floorplan "E:/20035024/count60/" "" "1.116 ns" { LessThan~623 q_bcd~3212 } "NODE_NAME" } "" } } { "cnt60.vhd" "" { Text "E:/20035024/count60/cnt60.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.237 ns) + CELL(0.442 ns) 5.018 ns q_bcd\[2\]~3221 5 COMB LC_X24_Y6_N8 1 " "Info: 5: + IC(1.237 ns) + CELL(0.442 ns) = 5.018 ns; Loc. = LC_X24_Y6_N8; Fanout = 1; COMB Node = 'q_bcd\[2\]~3221'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt60" "UNKNOWN" "V1" "E:/20035024/count60/db/cnt60.quartus_db" { Floorplan "E:/20035024/count60/" "" "1.679 ns" { q_bcd~3212 q_bcd[2]~3221 } "NODE_NAME" } "" } } { "cnt60.vhd" "" { Text "E:/20035024/count60/cnt60.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.555 ns) + CELL(0.292 ns) 6.865 ns q_bcd\[2\]~3222 6 COMB LC_X22_Y7_N9 1 " "Info: 6: + IC(1.555 ns) + CELL(0.292 ns) = 6.865 ns; Loc. = LC_X22_Y7_N9; Fanout = 1; COMB Node = 'q_bcd\[2\]~3222'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt60" "UNKNOWN" "V1" "E:/20035024/count60/db/cnt60.quartus_db" { Floorplan "E:/20035024/count60/" "" "1.847 ns" { q_bcd[2]~3221 q_bcd[2]~3222 } "NODE_NAME" } "" } } { "cnt60.vhd" "" { Text "E:/20035024/count60/cnt60.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.541 ns) + CELL(0.292 ns) 8.698 ns q_bcd\[2\]~3223 7 COMB LC_X24_Y5_N3 7 " "Info: 7: + IC(1.541 ns) + CELL(0.292 ns) = 8.698 ns; Loc. = LC_X24_Y5_N3; Fanout = 7; COMB Node = 'q_bcd\[2\]~3223'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt60" "UNKNOWN" "V1" "E:/20035024/count60/db/cnt60.quartus_db" { Floorplan "E:/20035024/count60/" "" "1.833 ns" { q_bcd[2]~3222 q_bcd[2]~3223 } "NODE_NAME" } "" } } { "cnt60.vhd" "" { Text "E:/20035024/count60/cnt60.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.518 ns) + CELL(0.442 ns) 9.658 ns Mux~396 8 COMB LC_X24_Y5_N2 1 " "Info: 8: + IC(0.518 ns) + CELL(0.442 ns) = 9.658 ns; Loc. = LC_X24_Y5_N2; Fanout = 1; COMB Node = 'Mux~396'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt60" "UNKNOWN" "V1" "E:/20035024/count60/db/cnt60.quartus_db" { Floorplan "E:/20035024/count60/" "" "0.960 ns" { q_bcd[2]~3223 Mux~396 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.073 ns) + CELL(2.108 ns) 14.839 ns led7s0\[0\] 9 PIN PIN_51 0 " "Info: 9: + IC(3.073 ns) + CELL(2.108 ns) = 14.839 ns; Loc. = PIN_51; Fanout = 0; PIN Node = 'led7s0\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt60" "UNKNOWN" "V1" "E:/20035024/count60/db/cnt60.quartus_db" { Floorplan "E:/20035024/count60/" "" "5.181 ns" { Mux~396 led7s0[0] } "NODE_NAME" } "" } } { "cnt60.vhd" "" { Text "E:/20035024/count60/cnt60.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.574 ns ( 30.82 % ) " "Info: Total cell delay = 4.574 ns ( 30.82 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.265 ns ( 69.18 % ) " "Info: Total interconnect delay = 10.265 ns ( 69.18 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt60" "UNKNOWN" "V1" "E:/20035024/count60/db/cnt60.quartus_db" { Floorplan "E:/20035024/count60/" "" "14.839 ns" { q_tmp[2] LessThan~622 LessThan~623 q_bcd~3212 q_bcd[2]~3221 q_bcd[2]~3222 q_bcd[2]~3223 Mux~396 led7s0[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "14.839 ns" { q_tmp[2] LessThan~622 LessThan~623 q_bcd~3212 q_bcd[2]~3221 q_bcd[2]~3222 q_bcd[2]~3223 Mux~396 led7s0[0] } { 0.000ns 1.266ns 0.401ns 0.674ns 1.237ns 1.555ns 1.541ns 0.518ns 3.073ns } { 0.000ns 0.114ns 0.442ns 0.442ns 0.442ns 0.292ns 0.292ns 0.442ns 2.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt60" "UNKNOWN" "V1" "E:/20035024/count60/db/cnt60.quartus_db" { Floorplan "E:/20035024/count60/" "" "2.781 ns" { clk q_tmp[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.781 ns" { clk clk~out0 q_tmp[2] } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt60" "UNKNOWN" "V1" "E:/20035024/count60/db/cnt60.quartus_db" { Floorplan "E:/20035024/count60/" "" "14.839 ns" { q_tmp[2] LessThan~622 LessThan~623 q_bcd~3212 q_bcd[2]~3221 q_bcd[2]~3222 q_bcd[2]~3223 Mux~396 led7s0[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "14.839 ns" { q_tmp[2] LessThan~622 LessThan~623 q_bcd~3212 q_bcd[2]~3221 q_bcd[2]~3222 q_bcd[2]~3223 Mux~396 led7s0[0] } { 0.000ns 1.266ns 0.401ns 0.674ns 1.237ns 1.555ns 1.541ns 0.518ns 3.073ns } { 0.000ns 0.114ns 0.442ns 0.442ns 0.442ns 0.292ns 0.292ns 0.442ns 2.108ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "q_tmp\[4\] en clk -6.749 ns register " "Info: th for register \"q_tmp\[4\]\" (data pin = \"en\", clock pin = \"clk\") is -6.749 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.781 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.781 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_93 8 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 8; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt60" "UNKNOWN" "V1" "E:/20035024/count60/db/cnt60.quartus_db" { Floorplan "E:/20035024/count60/" "" "" { clk } "NODE_NAME" } "" } } { "cnt60.vhd" "" { Text "E:/20035024/count60/cnt60.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.601 ns) + CELL(0.711 ns) 2.781 ns q_tmp\[4\] 2 REG LC_X23_Y7_N3 25 " "Info: 2: + IC(0.601 ns) + CELL(0.711 ns) = 2.781 ns; Loc. = LC_X23_Y7_N3; Fanout = 25; REG Node = 'q_tmp\[4\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt60" "UNKNOWN" "V1" "E:/20035024/count60/db/cnt60.quartus_db" { Floorplan "E:/20035024/count60/" "" "1.312 ns" { clk q_tmp[4] } "NODE_NAME" } "" } } { "cnt60.vhd" "" { Text "E:/20035024/count60/cnt60.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.39 % ) " "Info: Total cell delay = 2.180 ns ( 78.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.601 ns ( 21.61 % ) " "Info: Total interconnect delay = 0.601 ns ( 21.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt60" "UNKNOWN" "V1" "E:/20035024/count60/db/cnt60.quartus_db" { Floorplan "E:/20035024/count60/" "" "2.781 ns" { clk q_tmp[4] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.781 ns" { clk clk~out0 q_tmp[4] } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "cnt60.vhd" "" { Text "E:/20035024/count60/cnt60.vhd" 21 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.545 ns - Shortest pin register " "Info: - Shortest pin to register delay is 9.545 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns en 1 PIN PIN_11 8 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_11; Fanout = 8; PIN Node = 'en'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt60" "UNKNOWN" "V1" "E:/20035024/count60/db/cnt60.quartus_db" { Floorplan "E:/20035024/count60/" "" "" { en } "NODE_NAME" } "" } } { "cnt60.vhd" "" { Text "E:/20035024/count60/cnt60.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(7.209 ns) + CELL(0.867 ns) 9.545 ns q_tmp\[4\] 2 REG LC_X23_Y7_N3 25 " "Info: 2: + IC(7.209 ns) + CELL(0.867 ns) = 9.545 ns; Loc. = LC_X23_Y7_N3; Fanout = 25; REG Node = 'q_tmp\[4\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt60" "UNKNOWN" "V1" "E:/20035024/count60/db/cnt60.quartus_db" { Floorplan "E:/20035024/count60/" "" "8.076 ns" { en q_tmp[4] } "NODE_NAME" } "" } } { "cnt60.vhd" "" { Text "E:/20035024/count60/cnt60.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.336 ns ( 24.47 % ) " "Info: Total cell delay = 2.336 ns ( 24.47 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.209 ns ( 75.53 % ) " "Info: Total interconnect delay = 7.209 ns ( 75.53 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt60" "UNKNOWN" "V1" "E:/20035024/count60/db/cnt60.quartus_db" { Floorplan "E:/20035024/count60/" "" "9.545 ns" { en q_tmp[4] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "9.545 ns" { en en~out0 q_tmp[4] } { 0.000ns 0.000ns 7.209ns } { 0.000ns 1.469ns 0.867ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt60" "UNKNOWN" "V1" "E:/20035024/count60/db/cnt60.quartus_db" { Floorplan "E:/20035024/count60/" "" "2.781 ns" { clk q_tmp[4] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.781 ns" { clk clk~out0 q_tmp[4] } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cnt60" "UNKNOWN" "V1" "E:/20035024/count60/db/cnt60.quartus_db" { Floorplan "E:/20035024/count60/" "" "9.545 ns" { en q_tmp[4] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "9.545 ns" { en en~out0 q_tmp[4] } { 0.000ns 0.000ns 7.209ns } { 0.000ns 1.469ns 0.867ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}