📄 fpga_seg7_v4.map.rpt
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; -- 4 input functions ; 15 ;
; -- 3 input functions ; 0 ;
; -- <=2 input functions ; 47 ;
; -- Combinational cells for routing ; 0 ;
; Logic elements by mode ; ;
; -- normal mode ; 24 ;
; -- arithmetic mode ; 38 ;
; Total registers ; 43 ;
; I/O pins ; 13 ;
; Maximum fan-out node ; clk ;
; Maximum fan-out ; 25 ;
; Total fan-out ; 265 ;
; Average fan-out ; 2.25 ;
+---------------------------------------------+-------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+-------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ;
+-------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------------------+
; |FPGA_SEG7_V4 ; 62 (0) ; 43 (0) ; 0 ; 0 ; 0 ; 0 ; 13 ; 0 ; |FPGA_SEG7_V4 ;
; |addcont:inst2| ; 8 (8) ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |FPGA_SEG7_V4|addcont:inst2 ;
; |bin27seg:inst1| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |FPGA_SEG7_V4|bin27seg:inst1 ;
; |lpm_counter0:inst4| ; 25 (0) ; 25 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |FPGA_SEG7_V4|lpm_counter0:inst4 ;
; |lpm_counter:lpm_counter_component| ; 25 (0) ; 25 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |FPGA_SEG7_V4|lpm_counter0:inst4|lpm_counter:lpm_counter_component ;
; |cntr_tnd:auto_generated| ; 25 (25) ; 25 (25) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |FPGA_SEG7_V4|lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_tnd:auto_generated ;
; |segmain:inst| ; 14 (14) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |FPGA_SEG7_V4|segmain:inst ;
; |subcont:inst3| ; 8 (8) ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |FPGA_SEG7_V4|subcont:inst3 ;
+-------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 43 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 18 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 0 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+--------------------------------------------------+
; Inverted Register Statistics ;
+----------------------------------------+---------+
; Inverted Register ; Fan out ;
+----------------------------------------+---------+
; subcont:inst3|time[4] ; 2 ;
; subcont:inst3|time[0] ; 2 ;
; subcont:inst3|time[1] ; 2 ;
; subcont:inst3|time[5] ; 2 ;
; subcont:inst3|time[2] ; 2 ;
; subcont:inst3|time[6] ; 2 ;
; subcont:inst3|time[3] ; 2 ;
; subcont:inst3|time[7] ; 2 ;
; Total number of inverted registers = 8 ; ;
+----------------------------------------+---------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------+
; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; No ; |FPGA_SEG7_V4|segmain:inst|ledcom[3] ;
; 4:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; No ; |FPGA_SEG7_V4|segmain:inst|dataout[3] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------+
+---------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: lpm_counter0:inst4|lpm_counter:lpm_counter_component ;
+------------------------+-------------+------------------------------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------+-------------+------------------------------------------------------------+
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; LPM_WIDTH ; 26 ; Integer ;
; LPM_DIRECTION ; UP ; Untyped ;
; LPM_MODULUS ; 0 ; Untyped ;
; LPM_AVALUE ; UNUSED ; Untyped ;
; LPM_SVALUE ; UNUSED ; Untyped ;
; LPM_PORT_UPDOWN ; PORT_UNUSED ; Untyped ;
; DEVICE_FAMILY ; Cyclone II ; Untyped ;
; CARRY_CHAIN ; MANUAL ; Untyped ;
; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ;
; NOT_GATE_PUSH_BACK ; ON ; NOT_GATE_PUSH_BACK ;
; CARRY_CNT_EN ; SMART ; Untyped ;
; LABWIDE_SCLR ; ON ; Untyped ;
; USE_NEW_VERSION ; TRUE ; Untyped ;
; CBXI_PARAMETER ; cntr_tnd ; Untyped ;
+------------------------+-------------+------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in G:/FPGA_SEG7_V4/FPGA_SEG7_V4.map.eqn.
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version
Info: Processing started: Wed Sep 26 10:01:18 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off FPGA_SEG7_V4 -c FPGA_SEG7_V4
Info: Found 1 design units, including 1 entities, in source file FPGA_SEG7_V4.bdf
Info: Found entity 1: FPGA_SEG7_V4
Info: Found 2 design units, including 1 entities, in source file segmain.vhd
Info: Found design unit 1: segmain-behav
Info: Found entity 1: segmain
Info: Found 2 design units, including 1 entities, in source file bin27seg.vhd
Info: Found design unit 1: bin27seg-bin27seg_arch
Info: Found entity 1: bin27seg
Info: Found 2 design units, including 1 entities, in source file addcont.vhd
Info: Found design unit 1: addcont-behav
Info: Found entity 1: addcont
Info: Found 2 design units, including 1 entities, in source file subcont.vhd
Info: Found design unit 1: subcont-behav
Info: Found entity 1: subcont
Info: Elaborating entity "FPGA_SEG7_V4" for the top level hierarchy
Info: Elaborating entity "segmain" for hierarchy "segmain:inst"
Warning: Using design file lpm_counter0.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
Info: Found entity 1: lpm_counter0
Info: Elaborating entity "lpm_counter0" for hierarchy "lpm_counter0:inst4"
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf
Info: Found entity 1: lpm_counter
Info: Elaborating entity "lpm_counter" for hierarchy "lpm_counter0:inst4|lpm_counter:lpm_counter_component"
Info: Found 1 design units, including 1 entities, in source file db/cntr_tnd.tdf
Info: Found entity 1: cntr_tnd
Info: Elaborating entity "cntr_tnd" for hierarchy "lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_tnd:auto_generated"
Info: Elaborating entity "addcont" for hierarchy "addcont:inst2"
Info: Elaborating entity "subcont" for hierarchy "subcont:inst3"
Info: Elaborating entity "bin27seg" for hierarchy "bin27seg:inst1"
Info (10425): VHDL Case Statement information at bin27seg.vhd(43): OTHERS choice is never selected
Info: Implemented 75 device resources after synthesis - the final resource count might be different
Info: Implemented 2 input pins
Info: Implemented 11 output pins
Info: Implemented 62 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning
Info: Processing ended: Wed Sep 26 10:01:20 2007
Info: Elapsed time: 00:00:02
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