fpga_seg7_v4.fit.summary

来自「FPGA应用如sd卡控制」· SUMMARY 代码 · 共 15 行

Fitter Status : Successful - Wed Sep 26 10:01:30 2007
Quartus II Version : 5.1 Build 216 03/06/2006 SP 2 SJ Full Version
Revision Name : FPGA_SEG7_V4
Top-level Entity Name : FPGA_SEG7_V4
Family : Cyclone II
Device : EP2C35F484C8
Timing Models : Final
Total logic elements : 62 / 33,216 ( < 1 % )
Total registers : 43
Total pins : 13 / 322 ( 4 % )
Total virtual pins : 0
Total memory bits : 0 / 483,840 ( 0 % )
Embedded Multiplier 9-bit elements : 0 / 70 ( 0 % )
Total PLLs : 0 / 4 ( 0 % )