fpga_seg7_v4.tan.rpt

FPGA应用如sd卡控制

+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP2C35F484C8       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk'                                                                                                                                                                                                                                                                                                                                                                            ;
+-----------------------------------------+-----------------------------------------------------+-----------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                                                    ; To                                                                                      ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+-----------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 238.89 MHz ( period = 4.186 ns )                    ; lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_tnd:auto_generated|safe_q[0]  ; lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_tnd:auto_generated|safe_q[24] ; clk        ; clk      ; None                        ; None                      ; 3.920 ns                ;
; N/A                                     ; 240.96 MHz ( period = 4.150 ns )                    ; lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_tnd:auto_generated|safe_q[1]  ; lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_tnd:auto_generated|safe_q[24] ; clk        ; clk      ; None                        ; None                      ; 3.884 ns                ;
; N/A                                     ; 243.90 MHz ( period = 4.100 ns )                    ; lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_tnd:auto_generated|safe_q[0]  ; lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_tnd:auto_generated|safe_q[23] ; clk        ; clk      ; None                        ; None                      ; 3.834 ns                ;
; N/A                                     ; 246.06 MHz ( period = 4.064 ns )                    ; lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_tnd:auto_generated|safe_q[1]  ; lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_tnd:auto_generated|safe_q[23] ; clk        ; clk      ; None                        ; None                      ; 3.798 ns                ;
; N/A                                     ; 246.06 MHz ( period = 4.064 ns )                    ; lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_tnd:auto_generated|safe_q[2]  ; lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_tnd:auto_generated|safe_q[24] ; clk        ; clk      ; None                        ; None                      ; 3.798 ns                ;
; N/A                                     ; 249.13 MHz ( period = 4.014 ns )                    ; lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_tnd:auto_generated|safe_q[0]  ; lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_tnd:auto_generated|safe_q[22] ; clk        ; clk      ; None                        ; None                      ; 3.748 ns                ;
; N/A                                     ; 251.38 MHz ( period = 3.978 ns )                    ; lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_tnd:auto_generated|safe_q[1]  ; lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_tnd:auto_generated|safe_q[22] ; clk        ; clk      ; None                        ; None                      ; 3.712 ns                ;