fpga_seg7_v4.tan.summary

FPGA应用如sd卡控制

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Timing Analyzer Summary
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Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 16.001 ns
From           : segmain:inst|comclk[1]
To             : leddata[4]
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 238.89 MHz ( period = 4.186 ns )
From           : lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_tnd:auto_generated|safe_q[0]
To             : lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_tnd:auto_generated|safe_q[24]
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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