enc_dec.map.qmsg

提供了一个硬判决的viterbi译码器（2

{ "Warning" "WSGN_SEARCH_FILE" "ACS_3.vhd 2 1 " "Warning: Using design file ACS_3.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ACS_3-a " "Info: Found design unit 1: ACS_3-a" {  } { { "ACS_3.vhd" "" { Text "E:/My viterbi/viterbi213/ACS_3.vhd" 21 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 ACS_3 " "Info: Found entity 1: ACS_3" {  } { { "ACS_3.vhd" "" { Text "E:/My viterbi/viterbi213/ACS_3.vhd" 9 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ACS_3 ACS_3:inst6 " "Info: Elaborating entity \"ACS_3\" for hierarchy \"ACS_3:inst6\"" {  } { { "enc_dec.bdf" "inst6" { Schematic "E:/My viterbi/viterbi213/enc_dec.bdf" { { 464 480 640 592 "inst6" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "reg_exchange:inst1\|w3\[0\] High " "Info: Power-up level of register \"reg_exchange:inst1\|w3\[0\]\" is not specified -- using power-up level of High to minimize register" {  } { { "reg_exchange.vhd" "" { Text "E:/My viterbi/viterbi213/reg_exchange.vhd" 40 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "reg_exchange:inst1\|w3\[0\] data_in VCC " "Warning: Reduced register \"reg_exchange:inst1\|w3\[0\]\" with stuck data_in port to stuck value VCC" {  } { { "reg_exchange.vhd" "" { Text "E:/My viterbi/viterbi213/reg_exchange.vhd" 40 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "reg_exchange:inst1\|w2\[0\] data_in GND " "Warning: Reduced register \"reg_exchange:inst1\|w2\[0\]\" with stuck data_in port to stuck value GND" {  } { { "reg_exchange.vhd" "" { Text "E:/My viterbi/viterbi213/reg_exchange.vhd" 40 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "reg_exchange:inst1\|w1\[0\] High " "Info: Power-up level of register \"reg_exchange:inst1\|w1\[0\]\" is not specified -- using power-up level of High to minimize register" {  } { { "reg_exchange.vhd" "" { Text "E:/My viterbi/viterbi213/reg_exchange.vhd" 40 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "reg_exchange:inst1\|w1\[0\] data_in VCC " "Warning: Reduced register \"reg_exchange:inst1\|w1\[0\]\" with stuck data_in port to stuck value VCC" {  } { { "reg_exchange.vhd" "" { Text "E:/My viterbi/viterbi213/reg_exchange.vhd" 40 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "reg_exchange:inst1\|w0\[0\] data_in GND " "Warning: Reduced register \"reg_exchange:inst1\|w0\[0\]\" with stuck data_in port to stuck value GND" {  } { { "reg_exchange.vhd" "" { Text "E:/My viterbi/viterbi213/reg_exchange.vhd" 40 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "reg_exchange:inst1\|w3\[1\] High " "Info: Power-up level of register \"reg_exchange:inst1\|w3\[1\]\" is not specified -- using power-up level of High to minimize register" {  } { { "reg_exchange.vhd" "" { Text "E:/My viterbi/viterbi213/reg_exchange.vhd" 40 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "reg_exchange:inst1\|w3\[1\] data_in VCC " "Warning: Reduced register \"reg_exchange:inst1\|w3\[1\]\" with stuck data_in port to stuck value VCC" {  } { { "reg_exchange.vhd" "" { Text "E:/My viterbi/viterbi213/reg_exchange.vhd" 40 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "reg_exchange:inst1\|w2\[1\] High " "Info: Power-up level of register \"reg_exchange:inst1\|w2\[1\]\" is not specified -- using power-up level of High to minimize register" {  } { { "reg_exchange.vhd" "" { Text "E:/My viterbi/viterbi213/reg_exchange.vhd" 40 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "reg_exchange:inst1\|w2\[1\] data_in VCC " "Warning: Reduced register \"reg_exchange:inst1\|w2\[1\]\" with stuck data_in port to stuck value VCC" {  } { { "reg_exchange.vhd" "" { Text "E:/My viterbi/viterbi213/reg_exchange.vhd" 40 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "reg_exchange:inst1\|w1\[1\] data_in GND " "Warning: Reduced register \"reg_exchange:inst1\|w1\[1\]\" with stuck data_in port to stuck value GND" {  } { { "reg_exchange.vhd" "" { Text "E:/My viterbi/viterbi213/reg_exchange.vhd" 40 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "reg_exchange:inst1\|w0\[1\] data_in GND " "Warning: Reduced register \"reg_exchange:inst1\|w0\[1\]\" with stuck data_in port to stuck value GND" {  } { { "reg_exchange.vhd" "" { Text "E:/My viterbi/viterbi213/reg_exchange.vhd" 40 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "oreg0\[1\] GND " "Warning: Pin \"oreg0\[1\]\" stuck at GND" {  } { { "enc_dec.bdf" "" { Schematic "E:/My viterbi/viterbi213/enc_dec.bdf" { { -72 1168 1344 -56 "oreg0\[9..0\]" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "oreg0\[0\] GND " "Warning: Pin \"oreg0\[0\]\" stuck at GND" {  } { { "enc_dec.bdf" "" { Schematic "E:/My viterbi/viterbi213/enc_dec.bdf" { { -72 1168 1344 -56 "oreg0\[9..0\]" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "oreg1\[1\] GND " "Warning: Pin \"oreg1\[1\]\" stuck at GND" {  } { { "enc_dec.bdf" "" { Schematic "E:/My viterbi/viterbi213/enc_dec.bdf" { { -40 1192 1368 -24 "oreg1\[9..0\]" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "oreg1\[0\] VCC " "Warning: Pin \"oreg1\[0\]\" stuck at VCC" {  } { { "enc_dec.bdf" "" { Schematic "E:/My viterbi/viterbi213/enc_dec.bdf" { { -40 1192 1368 -24 "oreg1\[9..0\]" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "oreg2\[1\] VCC " "Warning: Pin \"oreg2\[1\]\" stuck at VCC" {  } { { "enc_dec.bdf" "" { Schematic "E:/My viterbi/viterbi213/enc_dec.bdf" { { -16 1224 1400 0 "oreg2\[9..0\]" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "oreg2\[0\] GND " "Warning: Pin \"oreg2\[0\]\" stuck at GND" {  } { { "enc_dec.bdf" "" { Schematic "E:/My viterbi/viterbi213/enc_dec.bdf" { { -16 1224 1400 0 "oreg2\[9..0\]" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "oreg3\[1\] VCC " "Warning: Pin \"oreg3\[1\]\" stuck at VCC" {  } { { "enc_dec.bdf" "" { Schematic "E:/My viterbi/viterbi213/enc_dec.bdf" { { 24 1264 1440 40 "oreg3\[9..0\]" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "oreg3\[0\] VCC " "Warning: Pin \"oreg3\[0\]\" stuck at VCC" {  } { { "enc_dec.bdf" "" { Schematic "E:/My viterbi/viterbi213/enc_dec.bdf" { { 24 1264 1440 40 "oreg3\[9..0\]" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "218 " "Info: Implemented 218 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "76 " "Info: Implemented 76 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "139 " "Info: Implemented 139 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 25 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 25 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Oct 09 19:42:06 2006 " "Info: Processing ended: Mon Oct 09 19:42:06 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:25 " "Info: Elapsed time: 00:00:25" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}