📄 dec.tan.qmsg

📁 提供了一个硬判决的viterbi译码器（2
💻 QMSG
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{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register ACS_3:inst6\|om_3\[0\] register ACS_2:inst5\|om_2\[5\] 187.2 MHz 5.342 ns Internal " "Info: Clock \"clk\" has Internal fmax of 187.2 MHz between source register \"ACS_3:inst6\|om_3\[0\]\" and destination register \"ACS_2:inst5\|om_2\[5\]\" (period= 5.342 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.165 ns + Longest register register " "Info: + Longest register to register delay is 5.165 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ACS_3:inst6\|om_3\[0\] 1 REG LC_X18_Y9_N8 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X18_Y9_N8; Fanout = 7; REG Node = 'ACS_3:inst6\|om_3\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ACS_3:inst6|om_3[0] } "NODE_NAME" } } { "ACS_3.vhd" "" { Text "E:/viterbi213/ACS_3.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.040 ns) + CELL(0.341 ns) 1.381 ns ACS_2:inst5\|Add1~104COUT1_106 2 COMB LC_X17_Y6_N1 2 " "Info: 2: + IC(1.040 ns) + CELL(0.341 ns) = 1.381 ns; Loc. = LC_X17_Y6_N1; Fanout = 2; COMB Node = 'ACS_2:inst5\|Add1~104COUT1_106'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.381 ns" { ACS_3:inst6|om_3[0] ACS_2:inst5|Add1~104COUT1_106 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 709 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.365 ns) 1.746 ns ACS_2:inst5\|Add1~101 3 COMB LC_X17_Y6_N2 3 " "Info: 3: + IC(0.000 ns) + CELL(0.365 ns) = 1.746 ns; Loc. = LC_X17_Y6_N2; Fanout = 3; COMB Node = 'ACS_2:inst5\|Add1~101'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.365 ns" { ACS_2:inst5|Add1~104COUT1_106 ACS_2:inst5|Add1~101 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 709 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.814 ns) + CELL(0.443 ns) 3.003 ns ACS_2:inst5\|LessThan0~100 4 COMB LC_X18_Y6_N2 1 " "Info: 4: + IC(0.814 ns) + CELL(0.443 ns) = 3.003 ns; Loc. = LC_X18_Y6_N2; Fanout = 1; COMB Node = 'ACS_2:inst5\|LessThan0~100'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.257 ns" { ACS_2:inst5|Add1~101 ACS_2:inst5|LessThan0~100 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1547 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.058 ns) 3.061 ns ACS_2:inst5\|LessThan0~95 5 COMB LC_X18_Y6_N3 1 " "Info: 5: + IC(0.000 ns) + CELL(0.058 ns) = 3.061 ns; Loc. = LC_X18_Y6_N3; Fanout = 1; COMB Node = 'ACS_2:inst5\|LessThan0~95'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.058 ns" { ACS_2:inst5|LessThan0~100 ACS_2:inst5|LessThan0~95 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1547 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.130 ns) 3.191 ns ACS_2:inst5\|LessThan0~90 6 COMB LC_X18_Y6_N4 1 " "Info: 6: + IC(0.000 ns) + CELL(0.130 ns) = 3.191 ns; Loc. = LC_X18_Y6_N4; Fanout = 1; COMB Node = 'ACS_2:inst5\|LessThan0~90'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.130 ns" { ACS_2:inst5|LessThan0~95 ACS_2:inst5|LessThan0~90 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1547 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.449 ns) 3.640 ns ACS_2:inst5\|LessThan0~78 7 COMB LC_X18_Y6_N6 7 " "Info: 7: + IC(0.000 ns) + CELL(0.449 ns) = 3.640 ns; Loc. = LC_X18_Y6_N6; Fanout = 7; COMB Node = 'ACS_2:inst5\|LessThan0~78'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.449 ns" { ACS_2:inst5|LessThan0~90 ACS_2:inst5|LessThan0~78 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1547 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.986 ns) + CELL(0.539 ns) 5.165 ns ACS_2:inst5\|om_2\[5\] 8 REG LC_X17_Y8_N0 3 " "Info: 8: + IC(0.986 ns) + CELL(0.539 ns) = 5.165 ns; Loc. = LC_X17_Y8_N0; Fanout = 3; REG Node = 'ACS_2:inst5\|om_2\[5\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.525 ns" { ACS_2:inst5|LessThan0~78 ACS_2:inst5|om_2[5] } "NODE_NAME" } } { "ACS_2.vhd" "" { Text "E:/viterbi213/ACS_2.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.325 ns ( 45.01 % ) " "Info: Total cell delay = 2.325 ns ( 45.01 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.840 ns ( 54.99 % ) " "Info: Total interconnect delay = 2.840 ns ( 54.99 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.165 ns" { ACS_3:inst6|om_3[0] ACS_2:inst5|Add1~104COUT1_106 ACS_2:inst5|Add1~101 ACS_2:inst5|LessThan0~100 ACS_2:inst5|LessThan0~95 ACS_2:inst5|LessThan0~90 ACS_2:inst5|LessThan0~78 ACS_2:inst5|om_2[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.165 ns" { ACS_3:inst6|om_3[0] ACS_2:inst5|Add1~104COUT1_106 ACS_2:inst5|Add1~101 ACS_2:inst5|LessThan0~100 ACS_2:inst5|LessThan0~95 ACS_2:inst5|LessThan0~90 ACS_2:inst5|LessThan0~78 ACS_2:inst5|om_2[5] } { 0.000ns 1.040ns 0.000ns 0.814ns 0.000ns 0.000ns 0.000ns 0.986ns } { 0.000ns 0.341ns 0.365ns 0.443ns 0.058ns 0.130ns 0.449ns 0.539ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.011 ns - Smallest " "Info: - Smallest clock skew is -0.011 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.958 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.958 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 62 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 62; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dec.bdf" "" { Schematic "E:/viterbi213/dec.bdf" { { -64 -192 -24 -48 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.588 ns) + CELL(0.542 ns) 2.958 ns ACS_2:inst5\|om_2\[5\] 2 REG LC_X17_Y8_N0 3 " "Info: 2: + IC(1.588 ns) + CELL(0.542 ns) = 2.958 ns; Loc. = LC_X17_Y8_N0; Fanout = 3; REG Node = 'ACS_2:inst5\|om_2\[5\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.130 ns" { clk ACS_2:inst5|om_2[5] } "NODE_NAME" } } { "ACS_2.vhd" "" { Text "E:/viterbi213/ACS_2.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 46.32 % ) " "Info: Total cell delay = 1.370 ns ( 46.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.588 ns ( 53.68 % ) " "Info: Total interconnect delay = 1.588 ns ( 53.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.958 ns" { clk ACS_2:inst5|om_2[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.958 ns" { clk clk~out0 ACS_2:inst5|om_2[5] } { 0.000ns 0.000ns 1.588ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.969 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.969 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 62 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 62; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dec.bdf" "" { Schematic "E:/viterbi213/dec.bdf" { { -64 -192 -24 -48 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.599 ns) + CELL(0.542 ns) 2.969 ns ACS_3:inst6\|om_3\[0\] 2 REG LC_X18_Y9_N8 7 " "Info: 2: + IC(1.599 ns) + CELL(0.542 ns) = 2.969 ns; Loc. = LC_X18_Y9_N8; Fanout = 7; REG Node = 'ACS_3:inst6\|om_3\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.141 ns" { clk ACS_3:inst6|om_3[0] } "NODE_NAME" } } { "ACS_3.vhd" "" { Text "E:/viterbi213/ACS_3.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 46.14 % ) " "Info: Total cell delay = 1.370 ns ( 46.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.599 ns ( 53.86 % ) " "Info: Total interconnect delay = 1.599 ns ( 53.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.969 ns" { clk ACS_3:inst6|om_3[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.969 ns" { clk clk~out0 ACS_3:inst6|om_3[0] } { 0.000ns 0.000ns 1.599ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.958 ns" { clk ACS_2:inst5|om_2[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.958 ns" { clk clk~out0 ACS_2:inst5|om_2[5] } { 0.000ns 0.000ns 1.588ns } { 0.000ns 0.828ns 0.542ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.969 ns" { clk ACS_3:inst6|om_3[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.969 ns" { clk clk~out0 ACS_3:inst6|om_3[0] } { 0.000ns 0.000ns 1.599ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "ACS_3.vhd" "" { Text "E:/viterbi213/ACS_3.vhd" 30 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "ACS_2.vhd" "" { Text "E:/viterbi213/ACS_2.vhd" 30 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.165 ns" { ACS_3:inst6|om_3[0] ACS_2:inst5|Add1~104COUT1_106 ACS_2:inst5|Add1~101 ACS_2:inst5|LessThan0~100 ACS_2:inst5|LessThan0~95 ACS_2:inst5|LessThan0~90 ACS_2:inst5|LessThan0~78 ACS_2:inst5|om_2[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.165 ns" { ACS_3:inst6|om_3[0] ACS_2:inst5|Add1~104COUT1_106 ACS_2:inst5|Add1~101 ACS_2:inst5|LessThan0~100 ACS_2:inst5|LessThan0~95 ACS_2:inst5|LessThan0~90 ACS_2:inst5|LessThan0~78 ACS_2:inst5|om_2[5] } { 0.000ns 1.040ns 0.000ns 0.814ns 0.000ns 0.000ns 0.000ns 0.986ns } { 0.000ns 0.341ns 0.365ns 0.443ns 0.058ns 0.130ns 0.449ns 0.539ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.958 ns" { clk ACS_2:inst5|om_2[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.958 ns" { clk clk~out0 ACS_2:inst5|om_2[5] } { 0.000ns 0.000ns 1.588ns } { 0.000ns 0.828ns 0.542ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.969 ns" { clk ACS_3:inst6|om_3[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.969 ns" { clk clk~out0 ACS_3:inst6|om_3[0] } { 0.000ns 0.000ns 1.599ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "ACS_3:inst6\|om_3\[5\] inp\[0\] clk 8.830 ns register " "Info: tsu for register \"ACS_3:inst6\|om_3\[5\]\" (data pin = \"inp\[0\]\", clock pin = \"clk\") is 8.830 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.778 ns + Longest pin register " "Info: + Longest pin to register delay is 11.778 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns inp\[0\] 1 PIN PIN_W17 5 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_W17; Fanout = 5; PIN Node = 'inp\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { inp[0] } "NODE_NAME" } } { "dec.bdf" "" { Schematic "E:/viterbi213/dec.bdf" { { 168 -208 -40 184 "inp\[1..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.419 ns) + CELL(0.280 ns) 5.786 ns ACS_1:inst4\|mc_2~0 2 COMB LC_X19_Y5_N9 24 " "Info: 2: + IC(4.419 ns) + CELL(0.280 ns) = 5.786 ns; Loc. = LC_X19_Y5_N9; Fanout = 24; COMB Node = 'ACS_1:inst4\|mc_2~0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.699 ns" { inp[0] ACS_1:inst4|mc_2~0 } "NODE_NAME" } } { "ACS_1.vhd" "" { Text "E:/viterbi213/ACS_1.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.902 ns) + CELL(0.451 ns) 8.139 ns ACS_3:inst6\|Add1~98COUT1_100 3 COMB LC_X17_Y9_N1 2 " "Info: 3: + IC(1.902 ns) + CELL(0.451 ns) = 8.139 ns; Loc. = LC_X17_Y9_N1; Fanout = 2; COMB Node = 'ACS_3:inst6\|Add1~98COUT1_100'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.353 ns" { ACS_1:inst4|mc_2~0 ACS_3:inst6|Add1~98COUT1_100 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 709 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.365 ns) 8.504 ns ACS_3:inst6\|Add1~95 4 COMB LC_X17_Y9_N2 3 " "Info: 4: + IC(0.000 ns) + CELL(0.365 ns) = 8.504 ns; Loc. = LC_X17_Y9_N2; Fanout = 3; COMB Node = 'ACS_3:inst6\|Add1~95'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.365 ns" { ACS_3:inst6|Add1~98COUT1_100 ACS_3:inst6|Add1~95 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 709 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.780 ns) + CELL(0.443 ns) 9.727 ns ACS_3:inst6\|LessThan0~100 5 COMB LC_X18_Y9_N2 1 " "Info: 5: + IC(0.780 ns) + CELL(0.443 ns) = 9.727 ns; Loc. = LC_X18_Y9_N2; Fanout = 1; COMB Node = 'ACS_3:inst6\|LessThan0~100'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.223 ns" { ACS_3:inst6|Add1~95 ACS_3:inst6|LessThan0~100 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1547 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.058 ns) 9.785 ns ACS_3:inst6\|LessThan0~95 6 COMB LC_X18_Y9_N3 1 " "Info: 6: + IC(0.000 ns) + CELL(0.058 ns) = 9.785 ns; Loc. = LC_X18_Y9_N3; Fanout = 1; COMB Node = 'ACS_3:inst6\|LessThan0~95'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.058 ns" { ACS_3:inst6|LessThan0~100 ACS_3:inst6|LessThan0~95 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1547 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.130 ns) 9.915 ns ACS_3:inst6\|LessThan0~90 7 COMB LC_X18_Y9_N4 1 " "Info: 7: + IC(0.000 ns) + CELL(0.130 ns) = 9.915 ns; Loc. = LC_X18_Y9_N4; Fanout = 1; COMB Node = 'ACS_3:inst6\|LessThan0~90'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.130 ns" { ACS_3:inst6|LessThan0~95 ACS_3:inst6|LessThan0~90 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1547 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.449 ns) 10.364 ns ACS_3:inst6\|LessThan0~78 8 COMB LC_X18_Y9_N6 7 " "Info: 8: + IC(0.000 ns) + CELL(0.449 ns) = 10.364 ns; Loc. = LC_X18_Y9_N6; Fanout = 7; COMB Node = 'ACS_3:inst6\|LessThan0~78'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.449 ns" { ACS_3:inst6|LessThan0~90 ACS_3:inst6|LessThan0~78 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1547 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.956 ns) + CELL(0.458 ns) 11.778 ns ACS_3:inst6\|om_3\[5\] 9 REG LC_X17_Y8_N8 3 " "Info: 9: + IC(0.956 ns) + CELL(0.458 ns) = 11.778 ns; Loc. = LC_X17_Y8_N8; Fanout = 3; REG Node = 'ACS_3:inst6\|om_3\[5\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.414 ns" { ACS_3:inst6|LessThan0~78 ACS_3:inst6|om_3[5] } "NODE_NAME" } } { "ACS_3.vhd" "" { Text "E:/viterbi213/ACS_3.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.721 ns ( 31.59 % ) " "Info: Total cell delay = 3.721 ns ( 31.59 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.057 ns ( 68.41 % ) " "Info: Total interconnect delay = 8.057 ns ( 68.41 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.778 ns" { inp[0] ACS_1:inst4|mc_2~0 ACS_3:inst6|Add1~98COUT1_100 ACS_3:inst6|Add1~95 ACS_3:inst6|LessThan0~100 ACS_3:inst6|LessThan0~95 ACS_3:inst6|LessThan0~90 ACS_3:inst6|LessThan0~78 ACS_3:inst6|om_3[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "11.778 ns" { inp[0] inp[0]~out0 ACS_1:inst4|mc_2~0 ACS_3:inst6|Add1~98COUT1_100 ACS_3:inst6|Add1~95 ACS_3:inst6|LessThan0~100 ACS_3:inst6|LessThan0~95 ACS_3:inst6|LessThan0~90 ACS_3:inst6|LessThan0~78 ACS_3:inst6|om_3[5] } { 0.000ns 0.000ns 4.419ns 1.902ns 0.000ns 0.780ns 0.000ns 0.000ns 0.000ns 0.956ns } { 0.000ns 1.087ns 0.280ns 0.451ns 0.365ns 0.443ns 0.058ns 0.130ns 0.449ns 0.458ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "ACS_3.vhd" "" { Text "E:/viterbi213/ACS_3.vhd" 30 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.958 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.958 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 62 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 62; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dec.bdf" "" { Schematic "E:/viterbi213/dec.bdf" { { -64 -192 -24 -48 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.588 ns) + CELL(0.542 ns) 2.958 ns ACS_3:inst6\|om_3\[5\] 2 REG LC_X17_Y8_N8 3 " "Info: 2: + IC(1.588 ns) + CELL(0.542 ns) = 2.958 ns; Loc. = LC_X17_Y8_N8; Fanout = 3; REG Node = 'ACS_3:inst6\|om_3\[5\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.130 ns" { clk ACS_3:inst6|om_3[5] } "NODE_NAME" } } { "ACS_3.vhd" "" { Text "E:/viterbi213/ACS_3.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 46.32 % ) " "Info: Total cell delay = 1.370 ns ( 46.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.588 ns ( 53.68 % ) " "Info: Total interconnect delay = 1.588 ns ( 53.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.958 ns" { clk ACS_3:inst6|om_3[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.958 ns" { clk clk~out0 ACS_3:inst6|om_3[5] } { 0.000ns 0.000ns 1.588ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.778 ns" { inp[0] ACS_1:inst4|mc_2~0 ACS_3:inst6|Add1~98COUT1_100 ACS_3:inst6|Add1~95 ACS_3:inst6|LessThan0~100 ACS_3:inst6|LessThan0~95 ACS_3:inst6|LessThan0~90 ACS_3:inst6|LessThan0~78 ACS_3:inst6|om_3[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "11.778 ns" { inp[0] inp[0]~out0 ACS_1:inst4|mc_2~0 ACS_3:inst6|Add1~98COUT1_100 ACS_3:inst6|Add1~95 ACS_3:inst6|LessThan0~100 ACS_3:inst6|LessThan0~95 ACS_3:inst6|LessThan0~90 ACS_3:inst6|LessThan0~78 ACS_3:inst6|om_3[5] } { 0.000ns 0.000ns 4.419ns 1.902ns 0.000ns 0.780ns 0.000ns 0.000ns 0.000ns 0.956ns } { 0.000ns 1.087ns 0.280ns 0.451ns 0.365ns 0.443ns 0.058ns 0.130ns 0.449ns 0.458ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.958 ns" { clk ACS_3:inst6|om_3[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.958 ns" { clk clk~out0 ACS_3:inst6|om_3[5] } { 0.000ns 0.000ns 1.588ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk dec_out reg_exchange:inst\|w1\[9\] 8.512 ns register " "Info: tco from clock \"clk\" to destination pin \"dec_out\" through register \"reg_exchange:inst\|w1\[9\]\" is 8.512 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.974 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.974 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 62 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 62; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dec.bdf" "" { Schematic "E:/viterbi213/dec.bdf" { { -64 -192 -24 -48 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.604 ns) + CELL(0.542 ns) 2.974 ns reg_exchange:inst\|w1\[9\] 2 REG LC_X18_Y6_N8 3 " "Info: 2: + IC(1.604 ns) + CELL(0.542 ns) = 2.974 ns; Loc. = LC_X18_Y6_N8; Fanout = 3; REG Node = 'reg_exchange:inst\|w1\[9\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.146 ns" { clk reg_exchange:inst|w1[9] } "NODE_NAME" } } { "reg_exchange.vhd" "" { Text "E:/viterbi213/reg_exchange.vhd" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 46.07 % ) " "Info: Total cell delay = 1.370 ns ( 46.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.604 ns ( 53.93 % ) " "Info: Total interconnect delay = 1.604 ns ( 53.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.974 ns" { clk reg_exchange:inst|w1[9] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.974 ns" { clk clk~out0 reg_exchange:inst|w1[9] } { 0.000ns 0.000ns 1.604ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "reg_exchange.vhd" "" { Text "E:/viterbi213/reg_exchange.vhd" 40 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.382 ns + Longest register pin " "Info: + Longest register to pin delay is 5.382 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns reg_exchange:inst\|w1\[9\] 1 REG LC_X18_Y6_N8 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X18_Y6_N8; Fanout = 3; REG Node = 'reg_exchange:inst\|w1\[9\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { reg_exchange:inst|w1[9] } "NODE_NAME" } } { "reg_exchange.vhd" "" { Text "E:/viterbi213/reg_exchange.vhd" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.874 ns) + CELL(0.366 ns) 1.240 ns output_design:inst1\|dec_out~153 2 COMB LC_X17_Y6_N8 1 " "Info: 2: + IC(0.874 ns) + CELL(0.366 ns) = 1.240 ns; Loc. = LC_X17_Y6_N8; Fanout = 1; COMB Node = 'output_design:inst1\|dec_out~153'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.240 ns" { reg_exchange:inst|w1[9] output_design:inst1|dec_out~153 } "NODE_NAME" } } { "output_design.vhd" "" { Text "E:/viterbi213/output_design.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(2.404 ns) 5.382 ns dec_out 3 PIN PIN_AA19 0 " "Info: 3: + IC(1.738 ns) + CELL(2.404 ns) = 5.382 ns; Loc. = PIN_AA19; Fanout = 0; PIN Node = 'dec_out'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.142 ns" { output_design:inst1|dec_out~153 dec_out } "NODE_NAME" } } { "dec.bdf" "" { Schematic "E:/viterbi213/dec.bdf" { { 344 1424 1600 360 "dec_out" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.770 ns ( 51.47 % ) " "Info: Total cell delay = 2.770 ns ( 51.47 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.612 ns ( 48.53 % ) " "Info: Total interconnect delay = 2.612 ns ( 48.53 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.382 ns" { reg_exchange:inst|w1[9] output_design:inst1|dec_out~153 dec_out } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.382 ns" { reg_exchange:inst|w1[9] output_design:inst1|dec_out~153 dec_out } { 0.000ns 0.874ns 1.738ns } { 0.000ns 0.366ns 2.404ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.974 ns" { clk reg_exchange:inst|w1[9] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.974 ns" { clk clk~out0 reg_exchange:inst|w1[9] } { 0.000ns 0.000ns 1.604ns } { 0.000ns 0.828ns 0.542ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.382 ns" { reg_exchange:inst|w1[9] output_design:inst1|dec_out~153 dec_out } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.382 ns" { reg_exchange:inst|w1[9] output_design:inst1|dec_out~153 dec_out } { 0.000ns 0.874ns 1.738ns } { 0.000ns 0.366ns 2.404ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "ACS_0:inst3\|acs_0 reset clk -2.221 ns register " "Info: th for register \"ACS_0:inst3\|acs_0\" (data pin = \"reset\", clock pin = \"clk\") is -2.221 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.979 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.979 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 62 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 62; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dec.bdf" "" { Schematic "E:/viterbi213/dec.bdf" { { -64 -192 -24 -48 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.609 ns) + CELL(0.542 ns) 2.979 ns ACS_0:inst3\|acs_0 2 REG LC_X18_Y5_N8 9 " "Info: 2: + IC(1.609 ns) + CELL(0.542 ns) = 2.979 ns; Loc. = LC_X18_Y5_N8; Fanout = 9; REG Node = 'ACS_0:inst3\|acs_0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.151 ns" { clk ACS_0:inst3|acs_0 } "NODE_NAME" } } { "ACS_0.vhd" "" { Text "E:/viterbi213/ACS_0.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 45.99 % ) " "Info: Total cell delay = 1.370 ns ( 45.99 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.609 ns ( 54.01 % ) " "Info: Total interconnect delay = 1.609 ns ( 54.01 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.979 ns" { clk ACS_0:inst3|acs_0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.979 ns" { clk clk~out0 ACS_0:inst3|acs_0 } { 0.000ns 0.000ns 1.609ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" {  } { { "ACS_0.vhd" "" { Text "E:/viterbi213/ACS_0.vhd" 16 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.300 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns reset 1 PIN PIN_T14 62 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_T14; Fanout = 62; PIN Node = 'reset'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "dec.bdf" "" { Schematic "E:/viterbi213/dec.bdf" { { -48 -192 -24 -32 "reset" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.894 ns) + CELL(0.319 ns) 5.300 ns ACS_0:inst3\|acs_0 2 REG LC_X18_Y5_N8 9 " "Info: 2: + IC(3.894 ns) + CELL(0.319 ns) = 5.300 ns; Loc. = LC_X18_Y5_N8; Fanout = 9; REG Node = 'ACS_0:inst3\|acs_0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.213 ns" { reset ACS_0:inst3|acs_0 } "NODE_NAME" } } { "ACS_0.vhd" "" { Text "E:/viterbi213/ACS_0.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.406 ns ( 26.53 % ) " "Info: Total cell delay = 1.406 ns ( 26.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.894 ns ( 73.47 % ) " "Info: Total interconnect delay = 3.894 ns ( 73.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.300 ns" { reset ACS_0:inst3|acs_0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.300 ns" { reset reset~out0 ACS_0:inst3|acs_0 } { 0.000ns 0.000ns 3.894ns } { 0.000ns 1.087ns 0.319ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.979 ns" { clk ACS_0:inst3|acs_0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.979 ns" { clk clk~out0 ACS_0:inst3|acs_0 } { 0.000ns 0.000ns 1.609ns } { 0.000ns 0.828ns 0.542ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.300 ns" { reset ACS_0:inst3|acs_0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.300 ns" { reset reset~out0 ACS_0:inst3|acs_0 } { 0.000ns 0.000ns 3.894ns } { 0.000ns 1.087ns 0.319ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
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