enc_dec.tan.qmsg

提供了一个硬判决的viterbi译码器（2

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register tr_dff2:inst2\|out_outp\[1\] register ACS_2:inst5\|acs_2 169.43 MHz 5.902 ns Internal " "Info: Clock \"clk\" has Internal fmax of 169.43 MHz between source register \"tr_dff2:inst2\|out_outp\[1\]\" and destination register \"ACS_2:inst5\|acs_2\" (period= 5.902 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.732 ns + Longest register register " "Info: + Longest register to register delay is 5.732 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns tr_dff2:inst2\|out_outp\[1\] 1 REG LC_X21_Y27_N8 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X21_Y27_N8; Fanout = 6; REG Node = 'tr_dff2:inst2\|out_outp\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { tr_dff2:inst2|out_outp[1] } "NODE_NAME" } } { "tr_dff2.vhd" "" { Text "E:/My viterbi/viterbi213/tr_dff2.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.857 ns) + CELL(0.183 ns) 1.040 ns ACS_3:inst6\|mc_1~37 2 COMB LC_X17_Y27_N9 6 " "Info: 2: + IC(0.857 ns) + CELL(0.183 ns) = 1.040 ns; Loc. = LC_X17_Y27_N9; Fanout = 6; COMB Node = 'ACS_3:inst6\|mc_1~37'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.040 ns" { tr_dff2:inst2|out_outp[1] ACS_3:inst6|mc_1~37 } "NODE_NAME" } } { "ACS_3.vhd" "" { Text "E:/My viterbi/viterbi213/ACS_3.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.847 ns) + CELL(0.443 ns) 2.330 ns ACS_2:inst5\|Add0~102 3 COMB LC_X25_Y27_N2 2 " "Info: 3: + IC(0.847 ns) + CELL(0.443 ns) = 2.330 ns; Loc. = LC_X25_Y27_N2; Fanout = 2; COMB Node = 'ACS_2:inst5\|Add0~102'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.290 ns" { ACS_3:inst6|mc_1~37 ACS_2:inst5|Add0~102 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 709 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.058 ns) 2.388 ns ACS_2:inst5\|Add0~100 4 COMB LC_X25_Y27_N3 2 " "Info: 4: + IC(0.000 ns) + CELL(0.058 ns) = 2.388 ns; Loc. = LC_X25_Y27_N3; Fanout = 2; COMB Node = 'ACS_2:inst5\|Add0~100'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.058 ns" { ACS_2:inst5|Add0~102 ACS_2:inst5|Add0~100 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 709 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.130 ns) 2.518 ns ACS_2:inst5\|Add0~98 5 COMB LC_X25_Y27_N4 2 " "Info: 5: + IC(0.000 ns) + CELL(0.130 ns) = 2.518 ns; Loc. = LC_X25_Y27_N4; Fanout = 2; COMB Node = 'ACS_2:inst5\|Add0~98'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.130 ns" { ACS_2:inst5|Add0~100 ACS_2:inst5|Add0~98 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 709 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.449 ns) 2.967 ns ACS_2:inst5\|Add0~95 6 COMB LC_X25_Y27_N5 3 " "Info: 6: + IC(0.000 ns) + CELL(0.449 ns) = 2.967 ns; Loc. = LC_X25_Y27_N5; Fanout = 3; COMB Node = 'ACS_2:inst5\|Add0~95'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.449 ns" { ACS_2:inst5|Add0~98 ACS_2:inst5|Add0~95 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 709 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.504 ns) + CELL(0.451 ns) 3.922 ns ACS_2:inst5\|LessThan0~85COUT1_111 7 COMB LC_X24_Y27_N5 1 " "Info: 7: + IC(0.504 ns) + CELL(0.451 ns) = 3.922 ns; Loc. = LC_X24_Y27_N5; Fanout = 1; COMB Node = 'ACS_2:inst5\|LessThan0~85COUT1_111'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.955 ns" { ACS_2:inst5|Add0~95 ACS_2:inst5|LessThan0~85COUT1_111 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1547 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.365 ns) 4.287 ns ACS_2:inst5\|LessThan0~78 8 COMB LC_X24_Y27_N6 7 " "Info: 8: + IC(0.000 ns) + CELL(0.365 ns) = 4.287 ns; Loc. = LC_X24_Y27_N6; Fanout = 7; COMB Node = 'ACS_2:inst5\|LessThan0~78'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.365 ns" { ACS_2:inst5|LessThan0~85COUT1_111 ACS_2:inst5|LessThan0~78 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1547 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.222 ns) + CELL(0.223 ns) 5.732 ns ACS_2:inst5\|acs_2 9 REG LC_X19_Y26_N0 9 " "Info: 9: + IC(1.222 ns) + CELL(0.223 ns) = 5.732 ns; Loc. = LC_X19_Y26_N0; Fanout = 9; REG Node = 'ACS_2:inst5\|acs_2'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.445 ns" { ACS_2:inst5|LessThan0~78 ACS_2:inst5|acs_2 } "NODE_NAME" } } { "ACS_2.vhd" "" { Text "E:/My viterbi/viterbi213/ACS_2.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.302 ns ( 40.16 % ) " "Info: Total cell delay = 2.302 ns ( 40.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.430 ns ( 59.84 % ) " "Info: Total interconnect delay = 3.430 ns ( 59.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.732 ns" { tr_dff2:inst2|out_outp[1] ACS_3:inst6|mc_1~37 ACS_2:inst5|Add0~102 ACS_2:inst5|Add0~100 ACS_2:inst5|Add0~98 ACS_2:inst5|Add0~95 ACS_2:inst5|LessThan0~85COUT1_111 ACS_2:inst5|LessThan0~78 ACS_2:inst5|acs_2 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.732 ns" { tr_dff2:inst2|out_outp[1] ACS_3:inst6|mc_1~37 ACS_2:inst5|Add0~102 ACS_2:inst5|Add0~100 ACS_2:inst5|Add0~98 ACS_2:inst5|Add0~95 ACS_2:inst5|LessThan0~85COUT1_111 ACS_2:inst5|LessThan0~78 ACS_2:inst5|acs_2 } { 0.000ns 0.857ns 0.847ns 0.000ns 0.000ns 0.000ns 0.504ns 0.000ns 1.222ns } { 0.000ns 0.183ns 0.443ns 0.058ns 0.130ns 0.449ns 0.451ns 0.365ns 0.223ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.004 ns - Smallest " "Info: - Smallest clock skew is -0.004 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.913 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.913 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 65 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 65; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "enc_dec.bdf" "" { Schematic "E:/My viterbi/viterbi213/enc_dec.bdf" { { -64 -192 -24 -48 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.543 ns) + CELL(0.542 ns) 2.913 ns ACS_2:inst5\|acs_2 2 REG LC_X19_Y26_N0 9 " "Info: 2: + IC(1.543 ns) + CELL(0.542 ns) = 2.913 ns; Loc. = LC_X19_Y26_N0; Fanout = 9; REG Node = 'ACS_2:inst5\|acs_2'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.085 ns" { clk ACS_2:inst5|acs_2 } "NODE_NAME" } } { "ACS_2.vhd" "" { Text "E:/My viterbi/viterbi213/ACS_2.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 47.03 % ) " "Info: Total cell delay = 1.370 ns ( 47.03 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.543 ns ( 52.97 % ) " "Info: Total interconnect delay = 1.543 ns ( 52.97 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.913 ns" { clk ACS_2:inst5|acs_2 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.913 ns" { clk clk~out0 ACS_2:inst5|acs_2 } { 0.000ns 0.000ns 1.543ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.917 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.917 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 65 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 65; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "enc_dec.bdf" "" { Schematic "E:/My viterbi/viterbi213/enc_dec.bdf" { { -64 -192 -24 -48 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.547 ns) + CELL(0.542 ns) 2.917 ns tr_dff2:inst2\|out_outp\[1\] 2 REG LC_X21_Y27_N8 6 " "Info: 2: + IC(1.547 ns) + CELL(0.542 ns) = 2.917 ns; Loc. = LC_X21_Y27_N8; Fanout = 6; REG Node = 'tr_dff2:inst2\|out_outp\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.089 ns" { clk tr_dff2:inst2|out_outp[1] } "NODE_NAME" } } { "tr_dff2.vhd" "" { Text "E:/My viterbi/viterbi213/tr_dff2.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 46.97 % ) " "Info: Total cell delay = 1.370 ns ( 46.97 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.547 ns ( 53.03 % ) " "Info: Total interconnect delay = 1.547 ns ( 53.03 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.917 ns" { clk tr_dff2:inst2|out_outp[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.917 ns" { clk clk~out0 tr_dff2:inst2|out_outp[1] } { 0.000ns 0.000ns 1.547ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.913 ns" { clk ACS_2:inst5|acs_2 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.913 ns" { clk clk~out0 ACS_2:inst5|acs_2 } { 0.000ns 0.000ns 1.543ns } { 0.000ns 0.828ns 0.542ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.917 ns" { clk tr_dff2:inst2|out_outp[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.917 ns" { clk clk~out0 tr_dff2:inst2|out_outp[1] } { 0.000ns 0.000ns 1.547ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "tr_dff2.vhd" "" { Text "E:/My viterbi/viterbi213/tr_dff2.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "ACS_2.vhd" "" { Text "E:/My viterbi/viterbi213/ACS_2.vhd" 16 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.732 ns" { tr_dff2:inst2|out_outp[1] ACS_3:inst6|mc_1~37 ACS_2:inst5|Add0~102 ACS_2:inst5|Add0~100 ACS_2:inst5|Add0~98 ACS_2:inst5|Add0~95 ACS_2:inst5|LessThan0~85COUT1_111 ACS_2:inst5|LessThan0~78 ACS_2:inst5|acs_2 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.732 ns" { tr_dff2:inst2|out_outp[1] ACS_3:inst6|mc_1~37 ACS_2:inst5|Add0~102 ACS_2:inst5|Add0~100 ACS_2:inst5|Add0~98 ACS_2:inst5|Add0~95 ACS_2:inst5|LessThan0~85COUT1_111 ACS_2:inst5|LessThan0~78 ACS_2:inst5|acs_2 } { 0.000ns 0.857ns 0.847ns 0.000ns 0.000ns 0.000ns 0.504ns 0.000ns 1.222ns } { 0.000ns 0.183ns 0.443ns 0.058ns 0.130ns 0.449ns 0.451ns 0.365ns 0.223ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.913 ns" { clk ACS_2:inst5|acs_2 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.913 ns" { clk clk~out0 ACS_2:inst5|acs_2 } { 0.000ns 0.000ns 1.543ns } { 0.000ns 0.828ns 0.542ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.917 ns" { clk tr_dff2:inst2|out_outp[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.917 ns" { clk clk~out0 tr_dff2:inst2|out_outp[1] } { 0.000ns 0.000ns 1.547ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "ACS_1:inst4\|om_1\[5\] reset clk 3.492 ns register " "Info: tsu for register \"ACS_1:inst4\|om_1\[5\]\" (data pin = \"reset\", clock pin = \"clk\") is 3.492 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.395 ns + Longest pin register " "Info: + Longest pin to register delay is 6.395 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.972 ns) 0.972 ns reset 1 PIN PIN_E13 31 " "Info: 1: + IC(0.000 ns) + CELL(0.972 ns) = 0.972 ns; Loc. = PIN_E13; Fanout = 31; PIN Node = 'reset'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "enc_dec.bdf" "" { Schematic "E:/My viterbi/viterbi213/enc_dec.bdf" { { 56 -192 -24 72 "reset" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.553 ns) + CELL(0.870 ns) 6.395 ns ACS_1:inst4\|om_1\[5\] 2 REG LC_X23_Y26_N7 3 " "Info: 2: + IC(4.553 ns) + CELL(0.870 ns) = 6.395 ns; Loc. = LC_X23_Y26_N7; Fanout = 3; REG Node = 'ACS_1:inst4\|om_1\[5\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.423 ns" { reset ACS_1:inst4|om_1[5] } "NODE_NAME" } } { "ACS_1.vhd" "" { Text "E:/My viterbi/viterbi213/ACS_1.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.842 ns ( 28.80 % ) " "Info: Total cell delay = 1.842 ns ( 28.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.553 ns ( 71.20 % ) " "Info: Total interconnect delay = 4.553 ns ( 71.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.395 ns" { reset ACS_1:inst4|om_1[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.395 ns" { reset reset~out0 ACS_1:inst4|om_1[5] } { 0.000ns 0.000ns 4.553ns } { 0.000ns 0.972ns 0.870ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "ACS_1.vhd" "" { Text "E:/My viterbi/viterbi213/ACS_1.vhd" 30 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.913 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.913 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 65 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 65; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "enc_dec.bdf" "" { Schematic "E:/My viterbi/viterbi213/enc_dec.bdf" { { -64 -192 -24 -48 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.543 ns) + CELL(0.542 ns) 2.913 ns ACS_1:inst4\|om_1\[5\] 2 REG LC_X23_Y26_N7 3 " "Info: 2: + IC(1.543 ns) + CELL(0.542 ns) = 2.913 ns; Loc. = LC_X23_Y26_N7; Fanout = 3; REG Node = 'ACS_1:inst4\|om_1\[5\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.085 ns" { clk ACS_1:inst4|om_1[5] } "NODE_NAME" } } { "ACS_1.vhd" "" { Text "E:/My viterbi/viterbi213/ACS_1.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 47.03 % ) " "Info: Total cell delay = 1.370 ns ( 47.03 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.543 ns ( 52.97 % ) " "Info: Total interconnect delay = 1.543 ns ( 52.97 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.913 ns" { clk ACS_1:inst4|om_1[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.913 ns" { clk clk~out0 ACS_1:inst4|om_1[5] } { 0.000ns 0.000ns 1.543ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.395 ns" { reset ACS_1:inst4|om_1[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.395 ns" { reset reset~out0 ACS_1:inst4|om_1[5] } { 0.000ns 0.000ns 4.553ns } { 0.000ns 0.972ns 0.870ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.913 ns" { clk ACS_1:inst4|om_1[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.913 ns" { clk clk~out0 ACS_1:inst4|om_1[5] } { 0.000ns 0.000ns 1.543ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk enc_out1\[1\] conv_213:inst\|df\[2\] 8.526 ns register " "Info: tco from clock \"clk\" to destination pin \"enc_out1\[1\]\" through register \"conv_213:inst\|df\[2\]\" is 8.526 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.917 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.917 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 65 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 65; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "enc_dec.bdf" "" { Schematic "E:/My viterbi/viterbi213/enc_dec.bdf" { { -64 -192 -24 -48 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.547 ns) + CELL(0.542 ns) 2.917 ns conv_213:inst\|df\[2\] 2 REG LC_X24_Y27_N7 3 " "Info: 2: + IC(1.547 ns) + CELL(0.542 ns) = 2.917 ns; Loc. = LC_X24_Y27_N7; Fanout = 3; REG Node = 'conv_213:inst\|df\[2\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.089 ns" { clk conv_213:inst|df[2] } "NODE_NAME" } } { "conv_213.vhd" "" { Text "E:/My viterbi/viterbi213/conv_213.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 46.97 % ) " "Info: Total cell delay = 1.370 ns ( 46.97 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.547 ns ( 53.03 % ) " "Info: Total interconnect delay = 1.547 ns ( 53.03 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.917 ns" { clk conv_213:inst|df[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.917 ns" { clk clk~out0 conv_213:inst|df[2] } { 0.000ns 0.000ns 1.547ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "conv_213.vhd" "" { Text "E:/My viterbi/viterbi213/conv_213.vhd" 23 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.453 ns + Longest register pin " "Info: + Longest register to pin delay is 5.453 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns conv_213:inst\|df\[2\] 1 REG LC_X24_Y27_N7 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X24_Y27_N7; Fanout = 3; REG Node = 'conv_213:inst\|df\[2\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { conv_213:inst|df[2] } "NODE_NAME" } } { "conv_213.vhd" "" { Text "E:/My viterbi/viterbi213/conv_213.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.184 ns) + CELL(0.183 ns) 1.367 ns conv_213:inst\|outp\[1\]~4 2 COMB LC_X22_Y28_N2 2 " "Info: 2: + IC(1.184 ns) + CELL(0.183 ns) = 1.367 ns; Loc. = LC_X22_Y28_N2; Fanout = 2; COMB Node = 'conv_213:inst\|outp\[1\]~4'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.367 ns" { conv_213:inst|df[2] conv_213:inst|outp[1]~4 } "NODE_NAME" } } { "conv_213.vhd" "" { Text "E:/My viterbi/viterbi213/conv_213.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.682 ns) + CELL(2.404 ns) 5.453 ns enc_out1\[1\] 3 PIN PIN_F16 0 " "Info: 3: + IC(1.682 ns) + CELL(2.404 ns) = 5.453 ns; Loc. = PIN_F16; Fanout = 0; PIN Node = 'enc_out1\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.086 ns" { conv_213:inst|outp[1]~4 enc_out1[1] } "NODE_NAME" } } { "enc_dec.bdf" "" { Schematic "E:/My viterbi/viterbi213/enc_dec.bdf" { { -32 160 336 -16 "enc_out1\[1..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.587 ns ( 47.44 % ) " "Info: Total cell delay = 2.587 ns ( 47.44 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.866 ns ( 52.56 % ) " "Info: Total interconnect delay = 2.866 ns ( 52.56 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.453 ns" { conv_213:inst|df[2] conv_213:inst|outp[1]~4 enc_out1[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.453 ns" { conv_213:inst|df[2] conv_213:inst|outp[1]~4 enc_out1[1] } { 0.000ns 1.184ns 1.682ns } { 0.000ns 0.183ns 2.404ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.917 ns" { clk conv_213:inst|df[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.917 ns" { clk clk~out0 conv_213:inst|df[2] } { 0.000ns 0.000ns 1.547ns } { 0.000ns 0.828ns 0.542ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.453 ns" { conv_213:inst|df[2] conv_213:inst|outp[1]~4 enc_out1[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.453 ns" { conv_213:inst|df[2] conv_213:inst|outp[1]~4 enc_out1[1] } { 0.000ns 1.184ns 1.682ns } { 0.000ns 0.183ns 2.404ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "conv_213:inst\|df\[1\] reset clk -2.138 ns register " "Info: th for register \"conv_213:inst\|df\[1\]\" (data pin = \"reset\", clock pin = \"clk\") is -2.138 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.917 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.917 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 65 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 65; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "enc_dec.bdf" "" { Schematic "E:/My viterbi/viterbi213/enc_dec.bdf" { { -64 -192 -24 -48 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.547 ns) + CELL(0.542 ns) 2.917 ns conv_213:inst\|df\[1\] 2 REG LC_X24_Y27_N0 2 " "Info: 2: + IC(1.547 ns) + CELL(0.542 ns) = 2.917 ns; Loc. = LC_X24_Y27_N0; Fanout = 2; REG Node = 'conv_213:inst\|df\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.089 ns" { clk conv_213:inst|df[1] } "NODE_NAME" } } { "conv_213.vhd" "" { Text "E:/My viterbi/viterbi213/conv_213.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 46.97 % ) " "Info: Total cell delay = 1.370 ns ( 46.97 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.547 ns ( 53.03 % ) " "Info: Total interconnect delay = 1.547 ns ( 53.03 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.917 ns" { clk conv_213:inst|df[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.917 ns" { clk clk~out0 conv_213:inst|df[1] } { 0.000ns 0.000ns 1.547ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" {  } { { "conv_213.vhd" "" { Text "E:/My viterbi/viterbi213/conv_213.vhd" 23 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.155 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.155 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.972 ns) 0.972 ns reset 1 PIN PIN_E13 31 " "Info: 1: + IC(0.000 ns) + CELL(0.972 ns) = 0.972 ns; Loc. = PIN_E13; Fanout = 31; PIN Node = 'reset'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "enc_dec.bdf" "" { Schematic "E:/My viterbi/viterbi213/enc_dec.bdf" { { 56 -192 -24 72 "reset" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.960 ns) + CELL(0.223 ns) 5.155 ns conv_213:inst\|df\[1\] 2 REG LC_X24_Y27_N0 2 " "Info: 2: + IC(3.960 ns) + CELL(0.223 ns) = 5.155 ns; Loc. = LC_X24_Y27_N0; Fanout = 2; REG Node = 'conv_213:inst\|df\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.183 ns" { reset conv_213:inst|df[1] } "NODE_NAME" } } { "conv_213.vhd" "" { Text "E:/My viterbi/viterbi213/conv_213.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.195 ns ( 23.18 % ) " "Info: Total cell delay = 1.195 ns ( 23.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.960 ns ( 76.82 % ) " "Info: Total interconnect delay = 3.960 ns ( 76.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.155 ns" { reset conv_213:inst|df[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.155 ns" { reset reset~out0 conv_213:inst|df[1] } { 0.000ns 0.000ns 3.960ns } { 0.000ns 0.972ns 0.223ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.917 ns" { clk conv_213:inst|df[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.917 ns" { clk clk~out0 conv_213:inst|df[1] } { 0.000ns 0.000ns 1.547ns } { 0.000ns 0.828ns 0.542ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.155 ns" { reset conv_213:inst|df[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.155 ns" { reset reset~out0 conv_213:inst|df[1] } { 0.000ns 0.000ns 3.960ns } { 0.000ns 0.972ns 0.223ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}