ceshi.map.qmsg

提供了一个硬判决的viterbi译码器（2

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Oct 02 13:11:40 2006 " "Info: Processing started: Mon Oct 02 13:11:40 2006" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ceshi -c ceshi " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ceshi -c ceshi" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ceshi.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ceshi.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 ceshi " "Info: Found entity 1: ceshi" {  } { { "ceshi.bdf" "" { Schematic "E:/viterbi213/ceshi.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "ceshi " "Info: Elaborating entity \"ceshi\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "tr_dff2.vhd 2 1 " "Warning: Using design file tr_dff2.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 tr_dff2-a " "Info: Found design unit 1: tr_dff2-a" {  } { { "tr_dff2.vhd" "" { Text "E:/viterbi213/tr_dff2.vhd" 15 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 tr_dff2 " "Info: Found entity 1: tr_dff2" {  } { { "tr_dff2.vhd" "" { Text "E:/viterbi213/tr_dff2.vhd" 7 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tr_dff2 tr_dff2:inst1 " "Info: Elaborating entity \"tr_dff2\" for hierarchy \"tr_dff2:inst1\"" {  } { { "ceshi.bdf" "inst1" { Schematic "E:/viterbi213/ceshi.bdf" { { 184 432 616 280 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "conv_213.vhd 2 1 " "Warning: Using design file conv_213.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 conv_213-a " "Info: Found design unit 1: conv_213-a" {  } { { "conv_213.vhd" "" { Text "E:/viterbi213/conv_213.vhd" 18 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 conv_213 " "Info: Found entity 1: conv_213" {  } { { "conv_213.vhd" "" { Text "E:/viterbi213/conv_213.vhd" 9 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "conv_213 conv_213:inst " "Info: Elaborating entity \"conv_213\" for hierarchy \"conv_213:inst\"" {  } { { "ceshi.bdf" "inst" { Schematic "E:/viterbi213/ceshi.bdf" { { 200 240 368 296 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "10 " "Info: Implemented 10 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "2 " "Info: Implemented 2 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "5 " "Info: Implemented 5 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Oct 02 13:11:43 2006 " "Info: Processing ended: Mon Oct 02 13:11:43 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}