output_design.tan.rpt

提供了一个硬判决的viterbi译码器（2

Timing Analyzer report for output_design
Fri Oct 06 15:25:58 2006
Version 6.0 Build 178 04/27/2006 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. tpd
  5. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-----------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                     ;
+------------------------------+-------+---------------+-------------+-------+---------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time ; From  ; To      ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+-------+---------+------------+----------+--------------+
; Worst-case tpd               ; N/A   ; None          ; 8.686 ns    ; sout2 ; dec_out ; --         ; --       ; 0            ;
; Total number of failed paths ;       ;               ;             ;       ;         ;            ;          ; 0            ;
+------------------------------+-------+---------------+-------------+-------+---------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1S10F484C5       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                         ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+---------------------------------------------------------------+
; tpd                                                           ;
+-------+-------------------+-----------------+-------+---------+
; Slack ; Required P2P Time ; Actual P2P Time ; From  ; To      ;
+-------+-------------------+-----------------+-------+---------+
; N/A   ; None              ; 8.686 ns        ; sout2 ; dec_out ;
; N/A   ; None              ; 8.575 ns        ; sout3 ; dec_out ;
; N/A   ; None              ; 8.505 ns        ; sout0 ; dec_out ;
; N/A   ; None              ; 8.385 ns        ; sout1 ; dec_out ;
+-------+-------------------+-----------------+-------+---------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Fri Oct 06 15:25:57 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off output_design -c output_design --timing_analysis_only
Info: Longest tpd from source pin "sout2" to destination pin "dec_out" is 8.686 ns
    Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_F16; Fanout = 1; PIN Node = 'sout2'
    Info: 2: + IC(3.706 ns) + CELL(0.366 ns) = 5.159 ns; Loc. = LC_X7_Y30_N2; Fanout = 1; COMB Node = 'dec_out~153'
    Info: 3: + IC(1.123 ns) + CELL(2.404 ns) = 8.686 ns; Loc. = PIN_F17; Fanout = 0; PIN Node = 'dec_out'
    Info: Total cell delay = 3.857 ns ( 44.40 % )
    Info: Total interconnect delay = 4.829 ns ( 55.60 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings
    Info: Processing ended: Fri Oct 06 15:25:58 2006
    Info: Elapsed time: 00:00:02