conv_213.tan.rpt

提供了一个硬判决的viterbi译码器（2

; N/A   ; None         ; 1.950 ns   ; reset ; df[2] ; clk      ;
; N/A   ; None         ; 1.704 ns   ; inp   ; df[2] ; clk      ;
+-------+--------------+------------+-------+-------+----------+


+------------------------------------------------------------------+
; tco                                                              ;
+-------+--------------+------------+-------+---------+------------+
; Slack ; Required tco ; Actual tco ; From  ; To      ; From Clock ;
+-------+--------------+------------+-------+---------+------------+
; N/A   ; None         ; 7.659 ns   ; df[0] ; outp[0] ; clk        ;
; N/A   ; None         ; 7.436 ns   ; df[1] ; outp[0] ; clk        ;
; N/A   ; None         ; 7.351 ns   ; df[2] ; outp[0] ; clk        ;
; N/A   ; None         ; 6.957 ns   ; df[2] ; outp[1] ; clk        ;
; N/A   ; None         ; 6.847 ns   ; df[0] ; outp[1] ; clk        ;
+-------+--------------+------------+-------+---------+------------+


+--------------------------------------------------------------------+
; th                                                                 ;
+---------------+-------------+-----------+-------+-------+----------+
; Minimum Slack ; Required th ; Actual th ; From  ; To    ; To Clock ;
+---------------+-------------+-----------+-------+-------+----------+
; N/A           ; None        ; -1.594 ns ; inp   ; df[2] ; clk      ;
; N/A           ; None        ; -1.840 ns ; reset ; df[2] ; clk      ;
; N/A           ; None        ; -1.842 ns ; reset ; df[0] ; clk      ;
; N/A           ; None        ; -1.843 ns ; reset ; df[1] ; clk      ;
+---------------+-------------+-----------+-------+-------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Mon Oct 02 12:55:08 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off conv_213 -c conv_213 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 422.12 MHz between source register "df[1]" and destination register "df[0]"
    Info: fmax restricted to clock pin edge rate 2.369 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.613 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y30_N2; Fanout = 2; REG Node = 'df[1]'
            Info: 2: + IC(0.390 ns) + CELL(0.223 ns) = 0.613 ns; Loc. = LC_X1_Y30_N5; Fanout = 2; REG Node = 'df[0]'
            Info: Total cell delay = 0.223 ns ( 36.38 % )
            Info: Total interconnect delay = 0.390 ns ( 63.62 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.934 ns
                Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 3; CLK Node = 'clk'
                Info: 2: + IC(1.564 ns) + CELL(0.542 ns) = 2.934 ns; Loc. = LC_X1_Y30_N5; Fanout = 2; REG Node = 'df[0]'
                Info: Total cell delay = 1.370 ns ( 46.69 % )
                Info: Total interconnect delay = 1.564 ns ( 53.31 % )
            Info: - Longest clock path from clock "clk" to source register is 2.934 ns
                Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 3; CLK Node = 'clk'
                Info: 2: + IC(1.564 ns) + CELL(0.542 ns) = 2.934 ns; Loc. = LC_X1_Y30_N2; Fanout = 2; REG Node = 'df[1]'
                Info: Total cell delay = 1.370 ns ( 46.69 % )
                Info: Total interconnect delay = 1.564 ns ( 53.31 % )
        Info: + Micro clock to output delay of source is 0.156 ns
        Info: + Micro setup delay of destination is 0.010 ns
Info: tsu for register "df[1]" (data pin = "reset", clock pin = "clk") is 1.953 ns
    Info: + Longest pin to register delay is 4.877 ns
        Info: 1: + IC(0.000 ns) + CELL(1.234 ns) = 1.234 ns; Loc. = PIN_E20; Fanout = 3; PIN Node = 'reset'
        Info: 2: + IC(3.185 ns) + CELL(0.458 ns) = 4.877 ns; Loc. = LC_X1_Y30_N2; Fanout = 2; REG Node = 'df[1]'
        Info: Total cell delay = 1.692 ns ( 34.69 % )
        Info: Total interconnect delay = 3.185 ns ( 65.31 % )
    Info: + Micro setup delay of destination is 0.010 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.934 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 3; CLK Node = 'clk'
        Info: 2: + IC(1.564 ns) + CELL(0.542 ns) = 2.934 ns; Loc. = LC_X1_Y30_N2; Fanout = 2; REG Node = 'df[1]'
        Info: Total cell delay = 1.370 ns ( 46.69 % )
        Info: Total interconnect delay = 1.564 ns ( 53.31 % )
Info: tco from clock "clk" to destination pin "outp[0]" through register "df[0]" is 7.659 ns
    Info: + Longest clock path from clock "clk" to source register is 2.934 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 3; CLK Node = 'clk'
        Info: 2: + IC(1.564 ns) + CELL(0.542 ns) = 2.934 ns; Loc. = LC_X1_Y30_N5; Fanout = 2; REG Node = 'df[0]'
        Info: Total cell delay = 1.370 ns ( 46.69 % )
        Info: Total interconnect delay = 1.564 ns ( 53.31 % )
    Info: + Micro clock to output delay of source is 0.156 ns
    Info: + Longest register to pin delay is 4.569 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y30_N5; Fanout = 2; REG Node = 'df[0]'
        Info: 2: + IC(0.766 ns) + CELL(0.280 ns) = 1.046 ns; Loc. = LC_X1_Y30_N6; Fanout = 1; COMB Node = 'outp~1'
        Info: 3: + IC(1.119 ns) + CELL(2.404 ns) = 4.569 ns; Loc. = PIN_M16; Fanout = 0; PIN Node = 'outp[0]'
        Info: Total cell delay = 2.684 ns ( 58.74 % )
        Info: Total interconnect delay = 1.885 ns ( 41.26 % )
Info: th for register "df[2]" (data pin = "inp", clock pin = "clk") is -1.594 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.934 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 3; CLK Node = 'clk'
        Info: 2: + IC(1.564 ns) + CELL(0.542 ns) = 2.934 ns; Loc. = LC_X1_Y30_N8; Fanout = 3; REG Node = 'df[2]'
        Info: Total cell delay = 1.370 ns ( 46.69 % )
        Info: Total interconnect delay = 1.564 ns ( 53.31 % )
    Info: + Micro hold delay of destination is 0.100 ns
    Info: - Shortest pin to register delay is 4.628 ns
        Info: 1: + IC(0.000 ns) + CELL(1.234 ns) = 1.234 ns; Loc. = PIN_E19; Fanout = 1; PIN Node = 'inp'
        Info: 2: + IC(3.171 ns) + CELL(0.223 ns) = 4.628 ns; Loc. = LC_X1_Y30_N8; Fanout = 3; REG Node = 'df[2]'
        Info: Total cell delay = 1.457 ns ( 31.48 % )
        Info: Total interconnect delay = 3.171 ns ( 68.52 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Mon Oct 02 12:55:09 2006
    Info: Elapsed time: 00:00:02